Inventor · disambiguated record
Gabor Drasny
Also filed as: DRASNY GABOR
25 granted patents·1 pending application·73 citations·filing 2005–2021
95Inventor score
Top patents by PatentIndex Score
26 records- 0195US9251304B2Circuit design evaluation with compact multi-waveform representationsIBM·Filed 2014·Granted Feb 2, 2016·17 cites·20 claims
- 0292US9916407B2Phase algebra for analysis of hierarchical designsIBM·Filed 2015·Granted Mar 13, 2018·9 cites·11 claims
- 0391US9798844B2Phase algebra for analysis of hierarchical designsIBM·Filed 2015·Granted Oct 24, 2017·7 cites·9 claims
- 0490US10216881B2Phase algebra for analysis of hierarchical designsIBM·Filed 2017·Granted Feb 26, 2019·6 cites·9 claims
- 0584US10331822B2Clock-gating phase algebra for clock analysisIBM·Filed 2015·Granted Jun 25, 2019·2 cites·10 claims
- 0684US10325041B2Circuit design analyzerIBM·Filed 2015·Granted Jun 18, 2019·2 cites·8 claims
- 0783US9547732B2Static checking of asynchronous clock domain crossingsIBM·Filed 2014·Granted Jan 17, 2017·3 cites·13 claims
- 0880US7280055B2Method and apparatus for encoding binary data as a zero terminated stringIBM·Filed 2005·Granted Oct 9, 2007·12 cites·12 claims
- 0979US10325040B2Conditional phase algebra for clock analysisIBM·Filed 2014·Granted Jun 18, 2019·2 cites·12 claims
- 1071US10990725B2Clock-gating phase algebra for clock analysisIBM·Filed 2019·Granted Apr 27, 2021·0 cites·16 claims
- 1171US8230406B2Compiler option consistency checking during incremental hardware design language compilationCARBONE RICHARD L H·Filed 2006·Granted Jul 24, 2012·10 cites·16 claims
- 1267US10599792B2Circuit design analyzerIBM·Filed 2017·Granted Mar 24, 2020·0 cites·18 claims
- 1367US10552559B2Glitch-aware phase algebra for clock analysisIBM·Filed 2017·Granted Feb 4, 2020·0 cites·20 claims
- 1463US10515164B2Clock-gating phase algebra for clock analysisIBM·Filed 2014·Granted Dec 24, 2019·0 cites·10 claims
- 1563US9830412B2Glitch-aware phase algebra for clock analysisIBM·Filed 2014·Granted Nov 28, 2017·0 cites·12 claims
- 1662US10558782B2Phase algebra for virtual clock and mode extraction in hierarchical designsIBM·Filed 2019·Granted Feb 11, 2020·0 cites·20 claims
- 1762US10552558B2Conditional phase algebra for clock analysisIBM·Filed 2015·Granted Feb 4, 2020·0 cites·8 claims
- 1861US9536024B2Methods for static checking of asynchronous clock domain crossingsIBM·Filed 2015·Granted Jan 3, 2017·0 cites·7 claims
- 1961US7823097B2Unrolling hardware design generate statements in a source window debuggerIBM·Filed 2006·Granted Oct 26, 2010·2 cites·18 claims
- 2053US10318695B2Phase algebra for virtual clock and mode extraction in hierarchical designsIBM·Filed 2016·Granted Jun 11, 2019·0 cites·20 claims
- 2153US8713494B2Synthesizing VHDL multiple wait FSMS into RT level FSMS by preprocessingIBM·Filed 2013·Granted Apr 29, 2014·0 cites·9 claims
- 2253US8140313B2Techniques for modeling variables in subprograms of hardware description language programsDRASNY GABOR·Filed 2008·Granted Mar 20, 2012·1 cites·12 claims
- 2346US10503856B2Phase algebra for specifying clocks and modes in hierarchical designsIBM·Filed 2016·Granted Dec 10, 2019·0 cites·15 claims
- 2445US8495533B2Synthesizing VHDL multiple wait behavioral FSMs into RT level FSMs by preprocessingDRASNY GABOR·Filed 2006·Granted Jul 23, 2013·0 cites·17 claims
- 2544US2023074528A1Iterative design of an integrated circuit designIBM·Filed 2021·Application pending·0 cites
- 2642US7506287B2Method, system, and program product for pre-compile processing of hardware design language (HDL) source filesIBM·Filed 2006·Granted Mar 17, 2009·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →