Inventor · disambiguated record
Gautam Kavipurapu
Also filed as: KAVIPURAPU GAUTAM · KAVIPURAPU GAUTAM NAG
13 granted patents·4 pending applications·695 citations·filing 1997–2022
92Inventor score
Top patents by PatentIndex Score
17 records- 0194US6009488AComputer having packet-based interconnect channelMICROLINC LLC·Filed 1997·Granted Dec 28, 1999·553 cites·13 claims
- 0286US9984037B1Scheduler for a fine grained graph processorSYNAPTIC ENGINES LLC·Filed 2016·Granted May 29, 2018·8 cites·12 claims
- 0385US7439763B1Scalable shared network memory switch for an FPGAXILINX INC·Filed 2005·Granted Oct 21, 2008·18 cites·15 claims
- 0483US6584546B2Highly efficient design of storage array for use in first and second cache spaces and memory subsystemsFiled 2001·Granted Jun 24, 2003·33 cites·16 claims
- 0582US7236488B1Intelligent routing switching systemKAVIPURAPU GAUTAM·Filed 2002·Granted Jun 26, 2007·47 cites·1 claims
- 0677US7568074B1Time based data storage for shared network memory switchXILINX INC·Filed 2005·Granted Jul 28, 2009·11 cites·9 claims
- 0770US7301367B1Method and apparatus for providing a scheduler select multiplexerXILINX INC·Filed 2005·Granted Nov 27, 2007·6 cites·20 claims
- 0869US7730276B1Striping of data into memory of a network data switch to prevent read and write collisionsXILINX INC·Filed 2005·Granted Jun 1, 2010·6 cites·12 claims
- 0962US6504786B1High speed, scalable, dynamic integrated programmable switch (DIPS) deviceFiled 2000·Granted Jan 7, 2003·8 cites·11 claims
- 1058USRE45078EHighly efficient design of storage array utilizing multiple pointers to indicate valid and invalid lines for use in first and second cache spaces and memory subsystemsKAVIPURAPU GAUTAM NAG·Filed 2012·Granted Aug 12, 2014·1 cites·48 claims
- 1155US6901070B2Dynamically programmable integrated switching device using an asymmetric 5T1C cellFiled 2000·Granted May 31, 2005·3 cites·12 claims
- 1254US7996604B1Class queue for network data switch to identify data memory locations by arrival timeXILINX INC·Filed 2005·Granted Aug 9, 2011·1 cites·9 claims
- 1354US2014237174A1Highly Efficient Design of Storage Array Utilizing Multiple Cache Lines for Use in First and Second Cache Spaces and Memory SubsystemsNARADA SYSTEMS LLC·Filed 2014·Application pending·0 cites
- 1451US2018246847A1Highly efficient scheduler for a fine grained graph processorKAVIPURAPU GAUTAM·Filed 2018·Application pending·0 cites
- 1549US12242785B2Software to industrial device interfaceECTRON CORP·Filed 2022·Granted Mar 4, 2025·0 cites·20 claims
- 1640US2002042861A1Apparatus and method for implementing a variable block size cacheFiled 2001·Application pending·0 cites
- 1734US2016239461A1Reconfigurable graph processorSYNAPTIC ENGINES LLC·Filed 2016·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →