Inventor · disambiguated record
Gabriel Quan
Also filed as: QUAN GABRIEL
17 granted patents·3 pending applications·221 citations·filing 2002–2023
94Inventor score
Top patents by PatentIndex Score
20 records- 0195US9569574B1Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2014·Granted Feb 14, 2017·35 cites·19 claims
- 0295US7669157B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesALTERA CORP·Filed 2006·Granted Feb 23, 2010·28 cites·21 claims
- 0387US11093672B2Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2020·Granted Aug 17, 2021·2 cites·19 claims
- 0483US8589849B1Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesBORER TERRY·Filed 2007·Granted Nov 19, 2013·10 cites·30 claims
- 0583US6779169B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2002·Granted Aug 17, 2004·32 cites·24 claims
- 0682US7464362B1Method and apparatus for performing incremental compilationALTERA CORP·Filed 2006·Granted Dec 9, 2008·12 cites·17 claims
- 0779US7360190B1Method and apparatus for performing retiming on field programmable gate arraysALTERA CORP·Filed 2004·Granted Apr 15, 2008·25 cites·31 claims
- 0879US7257800B1Method and apparatus for performing logic replication in field programmable gate arraysALTERA CORP·Filed 2004·Granted Aug 14, 2007·28 cites·34 claims
- 0975US8250505B1Method and apparatus for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2009·Granted Aug 21, 2012·5 cites·17 claims
- 1074US7194720B1Method and apparatus for implementing soft constraints in tools used for designing systems on programmable logic devicesALTERA CORP·Filed 2003·Granted Mar 20, 2007·19 cites·26 claims
- 1171US10635772B1Method and apparatus for performing fast incremental physical design optimizationALTERA CORP·Filed 2016·Granted Apr 28, 2020·1 cites·8 claims
- 1270US8434044B1Specifying placement and routing constraints for security and redundancyGOLDMAN DAVID SAMUEL·Filed 2010·Granted Apr 30, 2013·4 cites·19 claims
- 1367US9754065B2Method and apparatus for implementing soft constraints in tools used for designing programmable logic devicesALTERA CORP·Filed 2013·Granted Sep 5, 2017·1 cites·20 claims
- 1467US7181717B1Method and apparatus for placement of components onto programmable logic devicesALTERA CORP·Filed 2004·Granted Feb 20, 2007·10 cites·16 claims
- 1566US8589838B1M/A for performing incremental compilation using top-down and bottom-up design approachesBORER TERRY·Filed 2012·Granted Nov 19, 2013·1 cites·24 claims
- 1663US7594204B1Method and apparatus for performing layout-driven optimizations on field programmable gate arraysALTERA CORP·Filed 2003·Granted Sep 22, 2009·8 cites·17 claims
- 1757US9122826B1Method and apparatus for performing compilation using multiple design flowsALTERA CORP·Filed 2013·Granted Sep 1, 2015·0 cites·24 claims
- 1856US2017337318A1Method and Apparatus for Implementing Soft Constraints in Tools Used for Designing Programmable Logic DevicesALTERA CORP·Filed 2017·Application pending·0 cites
- 1948US2023333826A1Fast fpga compilation through bitstream stitchingKINSNER MICHAEL·Filed 2023·Application pending·0 cites
- 2048US2023237231A1Modular Compilation Flows for a Programmable Logic DeviceINTEL CORP·Filed 2023·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →