Inventor · disambiguated record
Ganesh Venkataramanan
Also filed as: VENKATARAMANAN GANESH
15 granted patents·10 pending applications·48 citations·filing 2010–2022
88Inventor score
Top patents by PatentIndex Score
25 records- 0192US8656401B2Method and apparatus for prioritizing processor scheduler queue operationsVENKATARAMANAN GANESH·Filed 2011·Granted Feb 18, 2014·36 cites·22 claims
- 0291US11122678B2Packaged device having imbedded array of componentsTESLA INC·Filed 2020·Granted Sep 14, 2021·3 cites·14 claims
- 0376US11367680B2Electronic assembly having multiple substrate segmentsTESLA INC·Filed 2018·Granted Jun 21, 2022·2 cites·7 claims
- 0468US9727340B2Hybrid tag scheduler to broadcast scheduler entry tags for picked instructionsADVANCED MICRO DEVICES INC·Filed 2013·Granted Aug 8, 2017·2 cites·20 claims
- 0567US12261110B2Electronic assembly having multiple substrate segmentsTESLA INC·Filed 2022·Granted Mar 25, 2025·0 cites·5 claims
- 0663US8787058B2Selectable multi-way comparatorVENKATARAMANAN GANESH·Filed 2011·Granted Jul 22, 2014·3 cites·12 claims
- 0761US9483273B2Dependent instruction suppression in a load-operation instructionADVANCED MICRO DEVICES INC·Filed 2013·Granted Nov 1, 2016·1 cites·13 claims
- 0855US8990623B2Avoiding BIST and MBIST intrusion logic in critical timing pathsEATON CRAIG D·Filed 2010·Granted Mar 24, 2015·1 cites·11 claims
- 0950US2024357769A1Heterogenous multi-layer structureTESLA INC·Filed 2022·Application pending·0 cites
- 1049US9489206B2Dependent instruction suppressionADVANCED MICRO DEVICES INC·Filed 2013·Granted Nov 8, 2016·0 cites·17 claims
- 1147US11901310B2Electronic assemblyTESLA INC·Filed 2019·Granted Feb 13, 2024·0 cites·23 claims
- 1247US9582286B2Register file management for operations using a single physical register for both source and resultADVANCED MICRO DEVICES INC·Filed 2012·Granted Feb 28, 2017·0 cites·19 claims
- 1343US9176738B2Method and apparatus for fast decoding and enhancing execution speed of an instructionVENKATARAMANAN GANESH·Filed 2011·Granted Nov 3, 2015·0 cites·20 claims
- 1442US10241797B2Replay reduction by wakeup suppression using early miss indicationVENKATARAMANAN GANESH·Filed 2012·Granted Mar 26, 2019·0 cites·6 claims
- 1542US9170638B2Method and apparatus for providing early bypass detection to reduce power consumption while reading register files of a processorVENKATARAMANAN GANESH·Filed 2010·Granted Oct 27, 2015·0 cites·21 claims
- 1640US2013117543A1Low overhead operation latency aware schedulerVENKATARAMANAN GANESH·Filed 2011·Application pending·0 cites
- 1739US2012144174A1Multiflow method and apparatus for operation fusionTALPES EMIL·Filed 2010·Application pending·0 cites
- 1839US2012110594A1Load balancing when assigning operations in a processorTALPES EMIL·Filed 2010·Application pending·0 cites
- 1939US2012143885A1Hybrid sources preready determinationTALPES EMIL·Filed 2010·Application pending·0 cites
- 2038US2012144175A1Method and apparatus for an enhanced speed unified scheduler utilizing optypes for compact logicVENKATARAMANAN GANESH·Filed 2010·Application pending·0 cites
- 2137US2012005459A1Processor having increased performance and energy saving via move eliminationFLEISCHMAN JAY·Filed 2010·Application pending·0 cites
- 2235US2012144393A1Multi-issue unified integer schedulerVINH JAMES·Filed 2010·Application pending·0 cites
- 2334US2012144173A1Unified scheduler for a processor multi-pipeline execution unit and methodsBUTLER MIKE·Filed 2010·Application pending·0 cites
- 2432US8570783B2Low power content-addressable memory and methodVENKATARAMANAN GANESH·Filed 2010·Granted Oct 29, 2013·0 cites·30 claims
- 2532US2012137185A1Method and apparatus for performing a memory built-in self-test on a plurality of memory element arraysVENKATARAMANAN GANESH·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →