Inventor · disambiguated record
Gert Koebernik
Also filed as: KOEBERNIK GERT
5 granted patents·1 pending application·66 citations·filing 2007–2009
80Inventor score
Top patents by PatentIndex Score
6 records- 0188US7800943B2Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readingsQIMONDA AG·Filed 2008·Granted Sep 21, 2010·28 cites·25 claims
- 0282US7649779B2Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systemsQIMONDA AG·Filed 2007·Granted Jan 19, 2010·16 cites·71 claims
- 0380US7864579B2Integrated circuits having a controller to control a read operation and methods for operating the sameQIMONDA AG·Filed 2008·Granted Jan 4, 2011·15 cites·4 claims
- 0466US7796449B2Integrated circuit, method to program a memory cell array of an integrated circuit, and memory moduleQIMONDA AG·Filed 2009·Granted Sep 14, 2010·6 cites·26 claims
- 0543US7920430B2Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operationQIMONDA AG·Filed 2008·Granted Apr 5, 2011·1 cites·11 claims
- 0628US2008002452A1Method for setting a read voltage, and semiconductor circuit arrangementAUGUSTIN UWE·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →