Inventor · disambiguated record
Gerald Pasdast
Also filed as: PASDAST GERALD · PASDAST GERALD S
49 granted patents·19 pending applications·160 citations·filing 1999–2025
97Inventor score
Top patents by PatentIndex Score
68 records- 0197US12107060B2Microelectronic assemblies with inductors in direct bonding regionsINTEL CORP·Filed 2020·Granted Oct 1, 2024·5 cites·20 claims
- 0297US12062631B2Microelectronic assemblies with inductors in direct bonding regionsINTEL CORP·Filed 2020·Granted Aug 13, 2024·4 cites·20 claims
- 0397US11652059B2Composite interposer structure and method of providing sameINTEL CORP·Filed 2021·Granted May 16, 2023·5 cites·15 claims
- 0495US10552357B2Multichip package linkINTEL CORP·Filed 2017·Granted Feb 4, 2020·14 cites·25 claims
- 0594US10795853B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2017·Granted Oct 6, 2020·9 cites·24 claims
- 0693US11581282B2Serializer-deserializer die for high speed signal interconnectINTEL CORP·Filed 2018·Granted Feb 14, 2023·10 cites·8 claims
- 0792US11270947B2Composite interposer structure and method of providing sameINTEL CORP·Filed 2019·Granted Mar 8, 2022·5 cites·20 claims
- 0892US9692402B2Method, apparatus, system for centering in a high performance interconnectINTEL CORP·Filed 2014·Granted Jun 27, 2017·10 cites·23 claims
- 0991US12332826B2Die-to-die interconnectINTEL CORP·Filed 2022·Granted Jun 17, 2025·2 cites·20 claims
- 1091US11586579B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2021·Granted Feb 21, 2023·2 cites·24 claims
- 1191US10686582B1Clock phase compensation apparatus and methodINTEL CORP·Filed 2019·Granted Jun 16, 2020·17 cites·21 claims
- 1290US11094672B2Composite IC chips including a chiplet embedded within metallization layers of a host IC chipINTEL CORP·Filed 2019·Granted Aug 17, 2021·5 cites·20 claims
- 1390US10073808B2Multichip package linkINTEL CORP·Filed 2013·Granted Sep 11, 2018·11 cites·20 claims
- 1489US12406962B2Power delivery through capacitor-dies in a multi-layered microelectronic assemblyINTEL CORP·Filed 2021·Granted Sep 2, 2025·2 cites·20 claims
- 1589US9946676B2Multichip package linkINTEL CORP·Filed 2015·Granted Apr 17, 2018·8 cites·25 claims
- 1687US12481614B2Standard interfaces for die to die (D2D) interconnect stacksINTEL CORP·Filed 2022·Granted Nov 25, 2025·1 cites·20 claims
- 1787US12353305B2Compliance and debug testing of a die-to-die interconnectINTEL CORP·Filed 2022·Granted Jul 8, 2025·1 cites·20 claims
- 1886US12362284B2Composite interposer structure and method of providing sameINTEL CORP·Filed 2024·Granted Jul 15, 2025·0 cites·20 claims
- 1983US12014990B2Composite interposer structure and method of providing sameINTEL CORP·Filed 2023·Granted Jun 18, 2024·0 cites·20 claims
- 2083US11205630B2Vias in composite IC chip structuresINTEL CORP·Filed 2019·Granted Dec 21, 2021·3 cites·20 claims
- 2182US6326802B1On-die adaptive arrangements for continuous process, voltage and temperature compensationINTEL CORP·Filed 1999·Granted Dec 4, 2001·42 cites·23 claims
- 2278US2025253233A1Skip level vias in metallization layers for integrated circuit devicesINTEL CORP·Filed 2025·Application pending·0 cites
- 2377US12117960B2Approximate data bus inversion technique for latency sensitive applicationsINTEL CORP·Filed 2020·Granted Oct 15, 2024·1 cites·20 claims
- 2476US11899615B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2023·Granted Feb 13, 2024·0 cites·24 claims
- 2576US11003610B2Multichip package linkINTEL CORP·Filed 2020·Granted May 11, 2021·1 cites·20 claims
- 2675US12315794B2Skip level vias in metallization layers for integrated circuit devicesINTEL CORP·Filed 2022·Granted May 27, 2025·0 cites·12 claims
- 2775US2024355768A1Microelectronic assemblies with inductors in direct bonding regionsINTEL CORP·Filed 2024·Application pending·0 cites
- 2870US11367707B2Semiconductor package or structure with dual-sided interposers and memoryINTEL CORP·Filed 2018·Granted Jun 21, 2022·1 cites·25 claims
- 2969US12505065B2On-package die-to-die (D2D) interconnect for memory using universal chiplet interconnect express (UCIe) PHYINTEL CORP·Filed 2023·Granted Dec 23, 2025·0 cites·20 claims
- 3069US11749649B2Composite IC chips including a chiplet embedded within metallization layers of a host IC chipINTEL CORP·Filed 2021·Granted Sep 5, 2023·0 cites·20 claims
- 3167US11694986B2Vias in composite IC chip structuresINTEL CORP·Filed 2021·Granted Jul 4, 2023·0 cites·19 claims
- 3266US12306216B2Dynamic voltage regulator sensing for chiplet-based designsINTEL CORP·Filed 2022·Granted May 20, 2025·0 cites·19 claims
- 3365US11294852B2Multiple dies hardware processors and methodsINTEL CORP·Filed 2020·Granted Apr 5, 2022·0 cites·25 claims
- 3462US12288746B2Skip level vias in metallization layers for integrated circuit devicesINTEL CORP·Filed 2019·Granted Apr 29, 2025·0 cites·8 claims
- 3561US12499019B2Retimers to extend a die-to-die interconnectINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 3661US10461805B2Valid lane trainingINTEL CORP·Filed 2015·Granted Oct 29, 2019·1 cites·20 claims
- 3760US12500583B2Clock interpolation system for eye-centeringINTEL CORP·Filed 2022·Granted Dec 16, 2025·0 cites·20 claims
- 3860US12362306B2Clock-gating in die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Jul 15, 2025·0 cites·20 claims
- 3958US12468597B2Valid signal for latency sensitive die-to-die (D2D) interconnectsINTEL CORP·Filed 2022·Granted Nov 11, 2025·0 cites·21 claims
- 4057US10560081B2Method, apparatus, system for centering in a high performance interconnectINTEL CORP·Filed 2017·Granted Feb 11, 2020·0 cites·21 claims
- 4157US2024030172A1Three dimensional universal chiplet interconnect as on-package interconnectINTEL CORP·Filed 2023·Application pending·0 cites
- 4256US12321305B2Sideband interface for die-to-die interconnectsINTEL CORP·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 4355US12164319B2Dual loop voltage regulatorINTEL CORP·Filed 2020·Granted Dec 10, 2024·0 cites·20 claims
- 4454US12405912B2Link initialization training and bring up for die-to-die interconnectINTEL CORP·Filed 2022·Granted Sep 2, 2025·0 cites·20 claims
- 4554US2023258716A1Techniques to perform semiconductor testingINTEL CORP·Filed 2023·Application pending·0 cites
- 4653US12316343B2PHY-based retry techniques for die-to-die interfacesINTEL CORP·Filed 2021·Granted May 27, 2025·0 cites·23 claims
- 4752US12469820B2Fine-grained disaggregated server architectureINTEL CORP·Filed 2021·Granted Nov 11, 2025·0 cites·20 claims
- 4852US11336559B2Fast-lane routing for multi-chip packagesINTEL CORP·Filed 2018·Granted May 17, 2022·0 cites·22 claims
- 4952US2022327084A1Die-to-die interconnect protocol layerINTEL CORP·Filed 2022·Application pending·0 cites
- 5052US2025112660A1Bidirectional link with hybrid suppression circuitINTEL CORP·Filed 2023·Application pending·0 cites
Showing the top 50 of 68 patent records by PatentIndex Score.
Join the waitlist — get patent alerts
Get an alert when Gerald Pasdast files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →