Inventor · disambiguated record
Gerald George Pechanek
Also filed as: PECHANEK GERALD G · PECHANEK GERALD GEORGE
161 granted patents·2 pending applications·4,614 citations·filing 1980–2020
99Inventor score
Top patents by PatentIndex Score
163 records- 0196US7263624B2Methods and apparatus for power control in a scalable array of processor elementsALTERA CORP·Filed 2005·Granted Aug 28, 2007·48 cites·20 claims
- 0295US7581079B2Processor composed of memory nodes that execute memory access instructions and cooperate with execution nodes to execute function instructionsPECHANEK GERALD GEORGE·Filed 2006·Granted Aug 25, 2009·36 cites·29 claims
- 0395US6173389B1Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processorBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Jan 9, 2001·207 cites·22 claims
- 0494US7836317B2Methods and apparatus for power control in a scalable array of processor elementsALTERA CORP·Filed 2008·Granted Nov 16, 2010·37 cites·16 claims
- 0593US9015354B2Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architectureALTERA CORP·Filed 2014·Granted Apr 21, 2015·15 cites·20 claims
- 0693US8443169B2Interconnection network connecting operation-configurable nodes according to one or more levels of adjacency in multiple dimensions of communication in a multi-processor and a neural processorPECHANEK GERALD GEORGE·Filed 2011·Granted May 14, 2013·18 cites·24 claims
- 0793US6606699B2Merged control/process element processor for executing VLIW simplex instructions with SISD control/SIMD process mode bitBOPS INC·Filed 2001·Granted Aug 12, 2003·67 cites·3 claims
- 0892US7398347B1Methods and apparatus for dynamic instruction controlled reconfigurable register fileALTERA CORP·Filed 2004·Granted Jul 8, 2008·59 cites·34 claims
- 0992US6397324B1Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register fileBOPS INC·Filed 2000·Granted May 28, 2002·79 cites·34 claims
- 1091US8904152B2Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecturePITSIANIS NIKOS P·Filed 2011·Granted Dec 2, 2014·15 cites·20 claims
- 1191US7493474B1Methods and apparatus for transforming, loading, and executing super-set instructionsALTERA CORP·Filed 2004·Granted Feb 17, 2009·59 cites·17 claims
- 1291US6557094B2Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsBOPS INC·Filed 2001·Granted Apr 29, 2003·48 cites·35 claims
- 1391US6366999B1Methods and apparatus to support conditional execution in a VLIW-based array processor with subword executionBOPS INC·Filed 1999·Granted Apr 2, 2002·130 cites·9 claims
- 1491US6167502AMethod and apparatus for manifold array processingBILLIONS OF OPERATIONS PER SEC·Filed 1997·Granted Dec 26, 2000·148 cites·34 claims
- 1591US5483620ALearning machine synapse processor system apparatusIBM·Filed 1995·Granted Jan 9, 1996·154 cites·7 claims
- 1690US5682491ASelective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifierIBM·Filed 1994·Granted Oct 28, 1997·179 cites·21 claims
- 1789US6769056B2Methods and apparatus for manifold array processingPTS CORP·Filed 2002·Granted Jul 27, 2004·42 cites·30 claims
- 1889US6446191B1Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communicationBOPS INC·Filed 2000·Granted Sep 3, 2002·48 cites·25 claims
- 1988US9460048B2Methods and apparatus for creating and executing a packet of instructions organized according to data dependencies between adjacent instructions and utilizing networks based on adjacencies to transport data in response to execution of the instructionsPECHANEK GERALD GEORGE·Filed 2013·Granted Oct 4, 2016·9 cites·26 claims
- 2088US7072929B2Methods and apparatus for efficient complex long multiplication and covariance matrix implementationPTS CORP·Filed 2001·Granted Jul 4, 2006·45 cites·12 claims
- 2188US6128720ADistributed processing array with component processors performing customized interpretation of instructionsIBM·Filed 1997·Granted Oct 3, 2000·167 cites·23 claims
- 2288US6023753AManifold array processorBILLION OF OPERATIONS PER SECO·Filed 1997·Granted Feb 8, 2000·102 cites·28 claims
- 2388US5337395ASPIN: a sequential pipeline neurocomputerIBM·Filed 1991·Granted Aug 9, 1994·77 cites·39 claims
- 2488US4943984AData processing system parallel data bus having a single oscillator clocking apparatusIBM·Filed 1988·Granted Jul 24, 1990·99 cites·22 claims
- 2587US7962719B2Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architecturePITSIANIS NIKOS P·Filed 2008·Granted Jun 14, 2011·14 cites·21 claims
- 2687US7424594B2Efficient complex multiplication and fast fourier transform (FFT) implementation on the ManArray architectureALTERA CORP·Filed 2004·Granted Sep 9, 2008·35 cites·20 claims
- 2787US6321322B1Methods and apparatus for scalable instruction set architecture with dynamic compact instructionsBOPS INC·Filed 2000·Granted Nov 20, 2001·35 cites·20 claims
- 2887US6216223B1Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processorBILLIONS OF OPERATIONS PER SEC·Filed 1999·Granted Apr 10, 2001·122 cites·29 claims
- 2987US6151668AMethods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communicationBILLIONS OF OPERATIONS PER SEC·Filed 1998·Granted Nov 21, 2000·108 cites·41 claims
- 3086US8156311B2Interconnection networks and methods of construction thereof for efficiently sharing memory and processing in a multiprocessor wherein connections are made according to adjacency of nodes in a dimensionPECHANEK GERALD GEORGE·Filed 2010·Granted Apr 10, 2012·7 cites·20 claims
- 3186US7146487B2Methods and apparatus to support conditional execution in a VLIW-based array processor with subword executionALTERA CORP·Filed 2003·Granted Dec 5, 2006·29 cites·26 claims
- 3286US6760831B2Methods and apparatus to support conditional execution in a VLIW-based array processor with subword executionPTS CORP·Filed 2002·Granted Jul 6, 2004·29 cites·20 claims
- 3386US6622234B1Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructionsPTS CORP·Filed 2000·Granted Sep 16, 2003·37 cites·15 claims
- 3486US6467036B1Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processorBOPS INC·Filed 2000·Granted Oct 15, 2002·34 cites·24 claims
- 3585US8489858B2Methods and apparatus for scalable array processor interrupt detection and responseBARRY EDWIN FRANKLIN·Filed 2012·Granted Jul 16, 2013·5 cites·20 claims
- 3685US6954842B2Methods and apparatus to support conditional execution in a VLIW-based array processor with subword executionPTS CORP·Filed 2003·Granted Oct 11, 2005·28 cites·25 claims
- 3785US6405185B1Massively parallel array processorIBM·Filed 1995·Granted Jun 11, 2002·108 cites·4 claims
- 3885US5325464APyramid learning architecture neurocomputerIBM·Filed 1993·Granted Jun 28, 1994·63 cites·32 claims
- 3985US4464070AMulti-character display controller for text recorderIBM·Filed 1982·Granted Aug 7, 1984·43 cites·19 claims
- 4084US6851041B2Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processorPTS CORP·Filed 2002·Granted Feb 1, 2005·29 cites·27 claims
- 4184US6842811B2Methods and apparatus for scalable array processor interrupt detection and responsePTS CORP·Filed 2001·Granted Jan 11, 2005·24 cites·22 claims
- 4284US6470441B1Methods and apparatus for manifold array processingBOPS INC·Filed 2000·Granted Oct 22, 2002·32 cites·7 claims
- 4384US6430677B2Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precisionBOPS INC·Filed 2001·Granted Aug 6, 2002·30 cites·16 claims
- 4484US5146543AScalable neural array processorIBM·Filed 1991·Granted Sep 8, 1992·58 cites·1 claims
- 4583US8341381B2Twisted and wrapped array organized into clusters of processing elementsPECHANEK GERALD GEORGE·Filed 2007·Granted Dec 25, 2012·7 cites·20 claims
- 4683USRE40883EMethods and apparatus for dynamic instruction controlled reconfigurable register file with extended precisionALTERA CORP·Filed 2004·Granted Aug 25, 2009·26 cites·23 claims
- 4783US5649135AParallel processing system and method using surrogate instructionsIBM·Filed 1995·Granted Jul 15, 1997·116 cites·23 claims
- 4882USRE41703EMethods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communicationALTERA CORP·Filed 2004·Granted Sep 14, 2010·24 cites·53 claims
- 4982US7685408B2Methods and apparatus for extracting bits of a source register based on a mask and right justifying the bits into a target registerALTERA CORP·Filed 2008·Granted Mar 23, 2010·11 cites·20 claims
- 5082US6965991B1Methods and apparatus for power control in a scalable array of processor elementsPTS CORP·Filed 2005·Granted Nov 15, 2005·10 cites·12 claims
Showing the top 50 of 163 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →