Inventor · disambiguated record
Gerald Strevig, Iii
Also filed as: STREVIG III GERALD · STREVIG III GERALD L
8 granted patents·13 citations·filing 2017–2021
77Inventor score
Files withIBM8
Top patents by PatentIndex Score
8 records- 0188US10902175B1Cross-hierarchical block pin placementIBM·Filed 2019·Granted Jan 26, 2021·8 cites·20 claims
- 0279US10943051B1Metal fill shape removal from selected netsIBM·Filed 2019·Granted Mar 9, 2021·4 cites·20 claims
- 0364US10372866B2Data processing system to implement wiring/silicon blockages via parameterized cellsIBM·Filed 2017·Granted Aug 6, 2019·1 cites·20 claims
- 0454US10943040B1Clock gating latch placementIBM·Filed 2019·Granted Mar 9, 2021·0 cites·20 claims
- 0553US10902178B1Wire orientation-based latch shuddlingIBM·Filed 2019·Granted Jan 26, 2021·0 cites·20 claims
- 0651US11875099B2Noise impact on function (NIOF) reduction for integrated circuit designIBM·Filed 2021·Granted Jan 16, 2024·0 cites·20 claims
- 0751US10831967B1Local clock buffer controller placement and connectivityIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 0849US11941340B2Cross-hierarchy antenna condition verificationIBM·Filed 2021·Granted Mar 26, 2024·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →