Inventor · disambiguated record
Gen Tsutsui
Also filed as: TSUTSUI GEN
38 granted patents·14 pending applications·81 citations·filing 2007–2024
96Inventor score
Top patents by PatentIndex Score
52 records- 0198US9721848B1Cutting fins and gates in CMOS devicesIBM·Filed 2016·Granted Aug 1, 2017·32 cites·20 claims
- 0294US10096713B1FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formationIBM·Filed 2017·Granted Oct 9, 2018·7 cites·10 claims
- 0392US10204828B1Enabling low resistance gates and contacts integrated with bilayer dielectricsIBM·Filed 2018·Granted Feb 12, 2019·8 cites·20 claims
- 0490US12119264B2Non-step nanosheet structure for stacked field-effect transistorsIBM·Filed 2022·Granted Oct 15, 2024·1 cites·13 claims
- 0585US10381479B2Interface charge reduction for SiGe surfaceIBM·Filed 2017·Granted Aug 13, 2019·3 cites·20 claims
- 0685US10032679B1Self-aligned doping in source/drain regions for low contact resistanceIBM·Filed 2017·Granted Jul 24, 2018·3 cites·18 claims
- 0784US10672910B2Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)IBM·Filed 2018·Granted Jun 2, 2020·3 cites·9 claims
- 0882US11037905B2Formation of stacked vertical transport field effect transistorsIBM·Filed 2019·Granted Jun 15, 2021·3 cites·12 claims
- 0982US10249758B2FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formationIBM·Filed 2017·Granted Apr 2, 2019·2 cites·9 claims
- 1081US11276781B2Bottom source/drain for fin field effect transistorsIBM·Filed 2020·Granted Mar 15, 2022·1 cites·19 claims
- 1181US8604546B1Reducing gate resistance in nonplanar multi-gate transistorBRYANT ANDRES·Filed 2012·Granted Dec 10, 2013·6 cites·20 claims
- 1278US10586767B2Hybrid BEOL metallization utilizing selective reflection maskIBM·Filed 2018·Granted Mar 10, 2020·2 cites·20 claims
- 1376US10535773B2FinFET with sigma recessed source/drain and un-doped buffer layer epitaxy for uniform junction formationIBM·Filed 2018·Granted Jan 14, 2020·1 cites·11 claims
- 1475US10535517B2Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOSIBM·Filed 2018·Granted Jan 14, 2020·1 cites·15 claims
- 1573US10115728B1Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared PFET and NFET trenchIBM·Filed 2017·Granted Oct 30, 2018·1 cites·17 claims
- 1670US11830946B2Bottom source/drain for fin field effect transistorsIBM·Filed 2022·Granted Nov 28, 2023·0 cites·20 claims
- 1769US10170477B2Forming MOSFET structures with work function modificationIBM·Filed 2015·Granted Jan 1, 2019·1 cites·13 claims
- 1867US8586437B2Semiconductor device and method of manufacturing the semiconductor deviceIWAMOTO TOSHIYUKI·Filed 2012·Granted Nov 19, 2013·2 cites·15 claims
- 1966US11183427B2Differing device characteristics on a single wafer by selective etchIBM·Filed 2020·Granted Nov 23, 2021·0 cites·19 claims
- 2066US10937648B2Gate stack designs for analog and logic devices in dual channel Si/SiGe CMOSIBM·Filed 2020·Granted Mar 2, 2021·0 cites·20 claims
- 2166US10892181B2Semiconductor device with mitigated local layout effectsIBM·Filed 2020·Granted Jan 12, 2021·0 cites·17 claims
- 2266US8269271B2Hybrid planarFET and FinFET provided on a chipIWAMOTO TOSHIYUKI·Filed 2010·Granted Sep 18, 2012·2 cites·9 claims
- 2365US11616140B2Vertical transport field effect transistor with bottom source/drainIBM·Filed 2021·Granted Mar 28, 2023·0 cites·20 claims
- 2465US11282962B2Threshold voltage adjustment from oxygen vacancy by scavenge metal filling at gate cut (CT)IBM·Filed 2020·Granted Mar 22, 2022·0 cites·13 claims
- 2565US10957646B2Hybrid BEOL metallization utilizing selective reflection maskIBM·Filed 2020·Granted Mar 23, 2021·0 cites·19 claims
- 2662US11056588B2Vertical transport field effect transistor with bottom source/drainIBM·Filed 2019·Granted Jul 6, 2021·0 cites·20 claims
- 2761US10971626B2Interface charge reduction for SiGe surfaceIBM·Filed 2019·Granted Apr 6, 2021·0 cites·16 claims
- 2860US10658224B2Method of fin oxidation by flowable oxide fill and steam anneal to mitigate local layout effectsIBM·Filed 2018·Granted May 19, 2020·0 cites·12 claims
- 2960US10312245B2Laser spike annealing for solid phase epitaxy and low contact resistance in an SRAM with a shared pFET and nFET trenchIBM·Filed 2018·Granted Jun 4, 2019·0 cites·20 claims
- 3060US2025287686A1Co-integration of different gate dielectric thicknesses with nanosheet technologyIBM·Filed 2024·Application pending·0 cites
- 3159US12446320B2Bottom contact with self-aligned spacer for stacked semiconductor devicesIBM·Filed 2022·Granted Oct 14, 2025·0 cites·16 claims
- 3259US2025089327A1Low external resistance last nanosheetIBM·Filed 2023·Application pending·0 cites
- 3358US10679901B2Differing device characteristics on a single wafer by selective etchIBM·Filed 2018·Granted Jun 9, 2020·0 cites·20 claims
- 3456US2024203991A1Structure and method to form a stack field effect transistor with different channel oriented gate-all-around devicesIBM·Filed 2022·Application pending·0 cites
- 3554US10685866B2Fin isolation to mitigate local layout effectsIBM·Filed 2018·Granted Jun 16, 2020·0 cites·13 claims
- 3654US8088677B2Method of manufacturing semiconductor device, and semiconductor deviceTSUTSUI GEN·Filed 2009·Granted Jan 3, 2012·2 cites·16 claims
- 3754US2024071811A1Stacked fet substrate contactIBM·Filed 2022·Application pending·0 cites
- 3853US10249542B2Self-aligned doping in source/drain regions for low contact resistanceIBM·Filed 2017·Granted Apr 2, 2019·0 cites·4 claims
- 3953US2024128346A1Gate-all-around transistors with dual pfet and nfet channelsIBM·Filed 2022·Application pending·0 cites
- 4052US12402352B2Unipolar-FET implementation in stacked-FET CMOSIBM·Filed 2021·Granted Aug 26, 2025·0 cites·11 claims
- 4152US2024088277A1Field effect transistor with channel capping layerIBM·Filed 2022·Application pending·0 cites
- 4251US2023317793A1Stacked field effect transistors with reduced gate-to-drain parasitic capacitanceIBM·Filed 2022·Application pending·0 cites
- 4351US2024088252A1Gate all around transistors with heterogeneous channelsIBM·Filed 2022·Application pending·0 cites
- 4449US10319811B2Semiconductor device including fin having condensed channel regionIBM·Filed 2015·Granted Jun 11, 2019·0 cites·16 claims
- 4549US10147725B2Forming MOSFET structures with work function modificationIBM·Filed 2015·Granted Dec 4, 2018·0 cites·7 claims
- 4647US9812556B2Semiconductor device and method of manufacturing the semiconductor deviceRENESAS ELECTRONICS CORP·Filed 2013·Granted Nov 7, 2017·0 cites·16 claims
- 4747US2017033184A1Semiconductor device including fin having condensed channel regionIBM·Filed 2015·Application pending·0 cites
- 4845US2008093699A1Semiconductor device and method of manufacturing the sameNEC ELECTRONICS CORP·Filed 2007·Application pending·0 cites
- 4945US2010117156A1Semiconductor device and method of manufacturing semiconductor deviceNEC ELECTRONICS CORP·Filed 2009·Application pending·0 cites
- 5044US2010123200A1Semiconductor device and method of manufacturing the sameNEC ELECTRONICS CORP·Filed 2009·Application pending·0 cites
Showing the top 50 of 52 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →