Inventor · disambiguated record
Gene F. Young
Also filed as: YOUNG GENE · YOUNG GENE F
13 granted patents·5 pending applications·375 citations·filing 1991–2025
93Inventor score
Top patents by PatentIndex Score
18 records- 0175US5359715AArchitectures for computer systems having multiple processors, multiple system buses and multiple I/O buses interfaced via multiple ported interfacesNCR CO·Filed 1991·Granted Oct 25, 1994·71 cites·14 claims
- 0270US11251576B2Circuit card with coherent interconnectINTEL CORP·Filed 2018·Granted Feb 15, 2022·2 cites·8 claims
- 0369US5991819ADual-ported memory controller which maintains cache coherency using a memory line status tableINTEL CORP·Filed 1996·Granted Nov 23, 1999·56 cites·9 claims
- 0464US5848434AMethod and apparatus for caching state information within a directory-based coherency memory systemINTEL CORP·Filed 1996·Granted Dec 8, 1998·47 cites·13 claims
- 0559US2024186206A1Integrated top side power delivery thermal technologyINTEL CORP·Filed 2024·Application pending·0 cites
- 0658US5809536AMethod for reducing the number of coherency cycles within a directory-based cache coherency memory system uitilizing a memory state cacheINTEL CORP INC·Filed 1996·Granted Sep 15, 1998·37 cites·3 claims
- 0758US5269005AMethod and apparatus for transferring data within a computer systemNCR CO·Filed 1991·Granted Dec 7, 1993·32 cites·16 claims
- 0857US5418914ARetry scheme for controlling transactions between two bussesNCR CORP·Filed 1993·Granted May 23, 1995·33 cites·4 claims
- 0954US6078997ADirectory-based coherency system for maintaining coherency in a dual-ported memory systemINTEL CORP·Filed 1996·Granted Jun 20, 2000·31 cites·2 claims
- 1053US10958003B2Interleaved card/riser connection assembly for compact card integrationINTEL CORP·Filed 2019·Granted Mar 23, 2021·0 cites·18 claims
- 1153US5790394ADual AC power supply input moduleNCR CORPORTION·Filed 1996·Granted Aug 4, 1998·40 cites·5 claims
- 1244US2025324546A1Cooling configuration for memory device and related computer systemINTEL CORP·Filed 2025·Application pending·0 cites
- 1341US5454082ASystem for preventing an unselected controller from transferring data via a first bus while concurrently permitting it to transfer data via a second busNCR CORP·Filed 1992·Granted Sep 26, 1995·13 cites·3 claims
- 1440US2002075860A1High density serverlets utilizing high speed data busFiled 2000·Application pending·0 cites
- 1537US5860120ADirectory-based coherency system using two bits to maintain coherency on a dual ported memory systemINTEL CORP·Filed 1996·Granted Jan 12, 1999·10 cites·6 claims
- 1634US2017215297A1Module with laterally translatable component platformINTEL CORP·Filed 2016·Application pending·0 cites
- 1732US2019121402A1Computer chassis with parallel backplanesINTEL CORP·Filed 2017·Application pending·0 cites
- 1829US5212799AMethod and apparatus for storing a data block in multiple memory banks within a computerNCR CO·Filed 1991·Granted May 18, 1993·3 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →