Inventor · disambiguated record
Ghasi R. Agrawal
Also filed as: AGRAWAL GHASI · AGRAWAL GHASI R
28 granted patents·479 citations·filing 1999–2008
97Inventor score
Top patents by PatentIndex Score
28 records- 0193US7260758B1Method and system for performing built-in self-test routines using an accumulator to store fault informationLSI CORP·Filed 2001·Granted Aug 21, 2007·73 cites·22 claims
- 0289US7493541B1Method and system for performing built-in-self-test routines using an accumulator to store fault informationLSI CORP·Filed 2007·Granted Feb 17, 2009·20 cites·26 claims
- 0389US6640321B1Built-in self-repair of semiconductor memory with redundant row testing using background patternLSI LOGIC CORP·Filed 2000·Granted Oct 28, 2003·63 cites·24 claims
- 0487US6643204B1Self-time scheme to reduce cycle time for memoriesLSI LOGIC CORP·Filed 2002·Granted Nov 4, 2003·39 cites·10 claims
- 0586US6483754B1Self-time scheme to reduce cycle time for memoriesLSI LOGIC CORP·Filed 2001·Granted Nov 19, 2002·35 cites·10 claims
- 0680US6871297B2Power-on state machine implementation with a counter to control the scan for products with hard-BISR memoriesLSI LOGIC CORP·Filed 2002·Granted Mar 22, 2005·28 cites·20 claims
- 0777US7076699B1Method for testing semiconductor devices having built-in self repair (BISR) memoryLSI LOGIC CORP·Filed 2001·Granted Jul 11, 2006·26 cites·18 claims
- 0875US6370078B1Way to compensate the effect of coupling between bitlines in a multi-port memoriesLSI LOGIC CORP·Filed 2000·Granted Apr 9, 2002·22 cites·29 claims
- 0974US6233197B1Multi-port semiconductor memory and compiler having capacitance compensationLSI LOGIC CORP·Filed 2000·Granted May 15, 2001·21 cites·11 claims
- 1073US6898143B2Sharing fuse blocks between memories in hard-BISRLSI LOGIC CORP·Filed 2003·Granted May 24, 2005·19 cites·24 claims
- 1172US6507524B1Integrated circuit memory having column redundancyLSI LOGIC CORP·Filed 2000·Granted Jan 14, 2003·19 cites·17 claims
- 1268US6928598B1Scan method for built-in-self-repair (BISR)LSI LOGIC CORP·Filed 2001·Granted Aug 9, 2005·14 cites·30 claims
- 1366US6366508B1Integrated circuit memory having column redundancy with no timing penaltyLSI LOGIC CORP·Filed 2000·Granted Apr 2, 2002·20 cites·15 claims
- 1464US6341092B1Designing memory for testability to support scan capability in an asic designLSI LOGIC CORP·Filed 2000·Granted Jan 22, 2002·13 cites·23 claims
- 1562US6870782B2Row redundancy memory repair scheme with shift to eliminate timing penaltyLSI LOGIC CORP·Filed 2003·Granted Mar 22, 2005·13 cites·13 claims
- 1659US6928591B2Fault repair controller for redundant memory integrated circuitsLSI LOGIC CORP·Filed 2002·Granted Aug 9, 2005·10 cites·15 claims
- 1758US7185243B1Testing implementation suitable for built-in self-repair (BISR) memoriesLSI LOGIC CORP·Filed 2001·Granted Feb 27, 2007·7 cites·16 claims
- 1857US7180819B1Converting dual port memory into 2 single port memoriesLSI LOGIC CORP·Filed 2005·Granted Feb 20, 2007·3 cites·20 claims
- 1950US6438046B1System and method for providing row redundancy with no timing penalty for built-in-self-repair (BISR) in high density memoriesLSI LOGIC CORP·Filed 2001·Granted Aug 20, 2002·6 cites·29 claims
- 2049US7272814B2Reconfiguring a RAM to a ROM using layers of metallizationLSI CORP·Filed 2004·Granted Sep 18, 2007·5 cites·16 claims
- 2148US6288598B1Laser fuse circuit designLSI LOGIC CORP·Filed 2000·Granted Sep 11, 2001·6 cites·12 claims
- 2248US6185140B1Sensing architecture with decreased precharge voltage levelsLSI LOGIC CORP·Filed 1999·Granted Feb 6, 2001·11 cites·1 claims
- 2347US7640152B2Accurate pin-based memory power model using arc-based characterizationLSI CORP·Filed 2008·Granted Dec 29, 2009·0 cites·7 claims
- 2445US7376541B2Accurate pin-based memory power model using arc-based characterizationLSI LOGIC CORP·Filed 2004·Granted May 20, 2008·1 cites·7 claims
- 2542US7913125B2BISR mode to test the redundant elements and regular functional memory to avoid test escapesLSI CORP·Filed 2003·Granted Mar 22, 2011·3 cites·10 claims
- 2640US6404700B1Low power high density asynchronous memory architectureLSI LOGIC CORP·Filed 2001·Granted Jun 11, 2002·2 cites·48 claims
- 2732US7536611B2Hard BISR scheme allowing field repair and usage of reliability controllerLST CORP·Filed 2003·Granted May 19, 2009·0 cites·17 claims
- 2832US7260700B2Method and apparatus for separating native, functional and test configurations of memoryLSI CORP·Filed 2004·Granted Aug 21, 2007·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →