Inventor · disambiguated record
Giuseppe Crisenza
Also filed as: CRISENZA GIUSEPPE · CRISENZA GIUSEPPE PAOLO
16 granted patents·341 citations·filing 1987–1999
95Inventor score
Top patents by PatentIndex Score
16 records- 0189US5717636AEEPROM memory with contactless memory cellsSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Feb 10, 1998·85 cites·39 claims
- 0276US5633822AMethod of programming a nonvolatile flash-EEPROM memory array using source line switching transistorsST MICROELECTRONICS SRL·Filed 1995·Granted May 27, 1997·34 cites·3 claims
- 0370US4808261AFabrication process for EPROM cells with oxide-nitride-oxide dielectricSGS MICROELETTRONICA SPA·Filed 1987·Granted Feb 28, 1989·27 cites·4 claims
- 0463US6187683B1Method for final passivation of integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1998·Granted Feb 13, 2001·28 cites·14 claims
- 0560US5587946AMethod of reading, erasing and programming a nonvolatile flash-EEPROM memory arrray using source line switching transistorsST MICROELECTRONICS SRL·Filed 1994·Granted Dec 24, 1996·17 cites·4 claims
- 0659US5464784AMethod of fabricating integrated devicesST MICROELECTRONICS SRL·Filed 1993·Granted Nov 7, 1995·17 cites·14 claims
- 0758US5543633AProcess and structure for measuring the planarity degree of a dielectric layer in an integrated circuit and integrated circuit including means for performing said processSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Aug 6, 1996·19 cites·16 claims
- 0856US5723350AProcess for fabricating a contactless electrical erasable EPROM memory deviceSGS THOMSON MICROELECTRONICS·Filed 1993·Granted Mar 3, 1998·17 cites·48 claims
- 0955US5798279AMethod of fabricating non-volatile memories with overlapping layersSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Aug 25, 1998·17 cites·16 claims
- 1052US5568418ANon-volatile memory in an integrated circuitSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Oct 22, 1996·14 cites·18 claims
- 1152US4719184AProcess for the fabrication of integrated structures including nonvolatile memory cells with layers of self-aligned silicon and associated transistorsSGS MICROELETTRONICA SPA·Filed 1987·Granted Jan 12, 1988·17 cites·2 claims
- 1250US5977586ANon-volatile integrated low-doped drain device with partially overlapping gate regionsST MICROELECTRONICS SRL·Filed 1995·Granted Nov 2, 1999·11 cites·9 claims
- 1347US6087729ALow dielectric constant composite film for integrated circuits of an inorganic aerogel and an organic filler grafted to the inorganic materialSGS THOMSON MICROELECTRONICS·Filed 1998·Granted Jul 11, 2000·14 cites·9 claims
- 1445US5707884AProcess for fabricating a contactless electrical erasable EPROM memory deviceSGS THOMSON MICROELECTRONICS·Filed 1995·Granted Jan 13, 1998·8 cites·4 claims
- 1541US6067250AMethod and apparatus for localizing point defects causing leakage currents in a non-volatile memory deviceST MICROELECTRONICS SRL·Filed 1999·Granted May 23, 2000·8 cites·6 claims
- 1639US4987088AFabrication of CMOS devices with reduced gate lengthST MICROELECTRONICS SRL·Filed 1989·Granted Jan 22, 1991·8 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →