Inventor · disambiguated record
Giuseppe Curello
Also filed as: CURELLO GIUSEPPE
16 granted patents·4 pending applications·340 citations·filing 2001–2016
94Inventor score
Top patents by PatentIndex Score
20 records- 0196US7335959B2Device with stepped source/drain region profileINTEL CORP·Filed 2005·Granted Feb 26, 2008·92 cites·24 claims
- 0296US7078325B2Process for producing a doped semiconductor substrateINFINEON TECHNOLOGIES AG·Filed 2001·Granted Jul 18, 2006·135 cites·17 claims
- 0394US7541239B2Selective spacer formation on transistors of different classes on the same deviceINTEL CORP·Filed 2006·Granted Jun 2, 2009·26 cites·14 claims
- 0493US7943468B2Penetrating implant for forming a semiconductor deviceINTEL CORP·Filed 2008·Granted May 17, 2011·20 cites·9 claims
- 0587US10332871B2Area-efficient and robust electrostatic discharge circuitINTEL IP CORP·Filed 2016·Granted Jun 25, 2019·8 cites·23 claims
- 0682US7422950B2Strained silicon MOS device with box layer between the source and drain regionsINTEL CORP·Filed 2005·Granted Sep 9, 2008·10 cites·13 claims
- 0775US7482670B2Enhancing strained device performance by use of multi narrow section layoutINTEL CORP·Filed 2006·Granted Jan 27, 2009·5 cites·11 claims
- 0874US8174060B2Selective spacer formation on transistors of different classes on the same deviceCURELLO GIUSEPPE·Filed 2011·Granted May 8, 2012·3 cites·1 claims
- 0974US7560780B2Active region spacer for semiconductor devices and method to form the sameINTEL CORP·Filed 2005·Granted Jul 14, 2009·4 cites·4 claims
- 1069US6503844B2Notched gate configuration for high performance integrated circuitsINFINEON TECHNOLOGIES AG·Filed 2001·Granted Jan 7, 2003·13 cites·9 claims
- 1165US8154067B2Selective spacer formation on transistors of different classes on the same deviceCURELLO GIUSEPPE·Filed 2009·Granted Apr 10, 2012·2 cites·1 claims
- 1263US6838329B2High concentration indium fluorine retrograde wellsINTEL CORP·Filed 2003·Granted Jan 4, 2005·7 cites·18 claims
- 1362US8426927B2Penetrating implant for forming a semiconductor deviceCURELLO GIUSEPPE·Filed 2011·Granted Apr 23, 2013·1 cites·4 claims
- 1462US7101765B2Enhancing strained device performance by use of multi narrow section layoutINTEL CORP·Filed 2004·Granted Sep 5, 2006·8 cites·26 claims
- 1561US7129533B2High concentration indium fluorine retrograde wellsINTEL CORP·Filed 2003·Granted Oct 31, 2006·6 cites·14 claims
- 1652US8741720B2Penetrating implant for forming a semiconductor deviceCURELLO GIUSEPPE·Filed 2013·Granted Jun 3, 2014·0 cites·7 claims
- 1747US2008311720A1Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regionsHOFFMAN THOMAS·Filed 2008·Application pending·0 cites
- 1843US2006065937A1Short channel effect of MOS devices by retrograde well engineering using tilted dopant implantation into recessed source/drain regionsHOFFMANN THOMAS·Filed 2004·Application pending·0 cites
- 1939US2007132034A1Isolation body for semiconductor devices and method to form the sameCURELLO GIUSEPPE·Filed 2005·Application pending·0 cites
- 2036US2007145495A1Method of fabricating a MOSFET transistor having an anti-halo for modifying narrow width device performanceINTEL CORP·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →