Inventor · disambiguated record
Gin Yee
Also filed as: YEE GIN · YEE GIN S
28 granted patents·6 pending applications·585 citations·filing 2000–2025
97Inventor score
Files withSUN MICROSYSTEMS INC21APPLE INC5ADVANCED MICRO DEVICES INC1ATI TECHNOLOGIES INC1UNIV WASHINGTON1
Top patents by PatentIndex Score
34 records- 0196US9838025B1Method for reducing lock time in a closed loop clock signal generatorAPPLE INC·Filed 2016·Granted Dec 5, 2017·22 cites·20 claims
- 0291US6720813B1Dual edge-triggered flip-flop design with asynchronous programmable resetSUN MICROSYSTEMS INC·Filed 2003·Granted Apr 13, 2004·46 cites·19 claims
- 0390US10521391B1Chip to chip interface with scalable bandwidthAPPLE INC·Filed 2018·Granted Dec 31, 2019·5 cites·20 claims
- 0490US7129800B2Compensation technique to mitigate aging effects in integrated circuit componentsSUN MICROSYSTEMS INC·Filed 2004·Granted Oct 31, 2006·43 cites·16 claims
- 0590US6510545B1Automated shielding algorithm for dynamic circuitsSUN MICROSYSTEMS INC·Filed 2000·Granted Jan 21, 2003·128 cites·25 claims
- 0689US6812758B2Negative bias temperature instability correction technique for delay locked loop and phase locked loop bias generatorsSUN MICROSYSTEMS INC·Filed 2003·Granted Nov 2, 2004·39 cites·15 claims
- 0788US11215664B1Non-invasive on-chip power measurement techniqueAPPLE INC·Filed 2020·Granted Jan 4, 2022·2 cites·20 claims
- 0885US6882196B2Duty cycle correctorSUN MICROSYSTEMS INC·Filed 2002·Granted Apr 19, 2005·30 cites·15 claims
- 0985US6549038B1Method of high-performance CMOS designUNIV WASHINGTON·Filed 2000·Granted Apr 15, 2003·38 cites·16 claims
- 1085US6265923B1Dual rail dynamic flip-flop with single evaluation pathSUN MICROSYSTEMS INC·Filed 2000·Granted Jul 24, 2001·31 cites·15 claims
- 1184US6934652B2On-chip temperature measurement techniqueSUN MICROSYSTEMS INC·Filed 2003·Granted Aug 23, 2005·32 cites·20 claims
- 1284US6686785B2Deskewing global clock skew using localized DLLsSUN MICROSYSTEMS INC·Filed 2001·Granted Feb 3, 2004·37 cites·12 claims
- 1379US7663398B1Circuit and method for high impedance input/output termination in shut off mode and for negative signal swingADVANCED MICRO DEVICES INC·Filed 2008·Granted Feb 16, 2010·8 cites·20 claims
- 1476US11023403B2Chip to chip interface with scalable bandwidthAPPLE INC·Filed 2019·Granted Jun 1, 2021·1 cites·20 claims
- 1574US7688925B2Bit-deskewing IO method and systemATI TECHNOLOGIES INC·Filed 2005·Granted Mar 30, 2010·8 cites·29 claims
- 1673US7054787B2Embedded integrated circuit aging sensor systemSUN MICROSYSTEMS INC·Filed 2003·Granted May 30, 2006·16 cites·25 claims
- 1772US6976235B2Region-based voltage drop budgets for low-power designSUN MICROSYSTEMS INC·Filed 2002·Granted Dec 13, 2005·17 cites·10 claims
- 1872US6814485B2On-die thermal monitoring techniqueSUN MICROSYSTEMS INC·Filed 2003·Granted Nov 9, 2004·17 cites·25 claims
- 1970US6707320B2Clock detect indicatorSUN MICROSYSTEMS INC·Filed 2001·Granted Mar 16, 2004·14 cites·14 claims
- 2066US6662126B2Measuring skew using on-chip samplingSUN MICROSYSTEMS INC·Filed 2001·Granted Dec 9, 2003·12 cites·18 claims
- 2164US6441656B1Clock divider for analysis of all clock edgesSUN MICROSYSTEMS INC·Filed 2001·Granted Aug 27, 2002·9 cites·15 claims
- 2259US6529057B2Stretching, shortening, and/or removing a clock cycleSUN MICROSYSTEMS INC·Filed 2001·Granted Mar 4, 2003·10 cites·60 claims
- 2357US6971079B2Accuracy of timing analysis using region-based voltage drop budgetsSUN MICROSYSTEMS INC·Filed 2002·Granted Nov 29, 2005·5 cites·15 claims
- 2455US6642756B1Frequency multiplier designSUN MICROSYSTEMS INC·Filed 2002·Granted Nov 4, 2003·4 cites·15 claims
- 2552US6815991B2Clock frequency multiplierSUN MICROSYSTEMS INC·Filed 2003·Granted Nov 9, 2004·6 cites·6 claims
- 2649US2025283766A1Resistive sensor circuitAPPLE INC·Filed 2025·Application pending·0 cites
- 2747US6812755B2Variation reduction technique for charge pump transistor agingSUN MICROSYSTEMS INC·Filed 2003·Granted Nov 2, 2004·4 cites·20 claims
- 2842US7203613B1IC analog debugging and calibration thereofSUN MICROSYSTEMS INC·Filed 2004·Granted Apr 10, 2007·1 cites·18 claims
- 2942US2003037271A1Reducing clock skew by power supply isolationFiled 2001·Application pending·0 cites
- 3041US6993103B2Method for synchronizing clock and data signalsSUN MICROSYSTEMS INC·Filed 2001·Granted Jan 31, 2006·0 cites·16 claims
- 3141US2003101423A1Clock grid skew reduction using a wire tree architectureFiled 2001·Application pending·0 cites
- 3233US2004187086A1Single edge-triggered flip-flop design with asynchronous programmable resetFiled 2003·Application pending·0 cites
- 3333US2003098720A1Lock detect indicator for a phase locked loopFiled 2001·Application pending·0 cites
- 3432US2003163750A1Clock grid skew reduction technique using biasable delay driversFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →