Inventor · disambiguated record
Glenn D. Gilda
Also filed as: GILDA GLENN · GILDA GLENN D · GILDA GLENN DAVID
41 granted patents·1 pending application·430 citations·filing 1989–2022
98Inventor score
Files withIBM42
Top patents by PatentIndex Score
42 records- 0195US11200119B2Low latency availability in degraded redundant array of independent memoryIBM·Filed 2020·Granted Dec 14, 2021·4 cites·19 claims
- 0292US6920519B1System and method for supporting access to multiple I/O hub nodes in a host bridgeIBM·Filed 2000·Granted Jul 19, 2005·81 cites·32 claims
- 0391US9430418B2Synchronization and order detection in a memory systemIBM·Filed 2013·Granted Aug 30, 2016·11 cites·17 claims
- 0490US9495231B2Reestablishing synchronization in a memory systemIBM·Filed 2016·Granted Nov 15, 2016·6 cites·1 claims
- 0589US9146864B2Address mapping including generic bits for universal addressing independent of memory typeIBM·Filed 2013·Granted Sep 29, 2015·12 cites·19 claims
- 0687US11646861B2Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modesIBM·Filed 2021·Granted May 9, 2023·2 cites·25 claims
- 0787US9946595B2Reducing uncorrectable errors based on a history of correctable errorsIBM·Filed 2015·Granted Apr 17, 2018·4 cites·18 claims
- 0887US9594647B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Mar 14, 2017·4 cites·1 claims
- 0987US9318171B2Dual asynchronous and synchronous memory systemIBM·Filed 2014·Granted Apr 19, 2016·8 cites·12 claims
- 1087US9142272B2Dual asynchronous and synchronous memory systemIBM·Filed 2013·Granted Sep 22, 2015·9 cites·8 claims
- 1187US7934046B2Access table lookup for bus bridgeIBM·Filed 2008·Granted Apr 26, 2011·18 cites·20 claims
- 1286US10558519B2Power-reduced redundant array of independent memory (RAIM) systemIBM·Filed 2017·Granted Feb 11, 2020·4 cites·18 claims
- 1386US10296417B2Reducing uncorrectable errors based on a history of correctable errorsIBM·Filed 2018·Granted May 21, 2019·3 cites·14 claims
- 1480US11449397B2Cache array macro micro-maskingIBM·Filed 2019·Granted Sep 20, 2022·2 cites·25 claims
- 1580US9104564B2Early data delivery prior to error detection completionIBM·Filed 2014·Granted Aug 11, 2015·4 cites·12 claims
- 1677US9136987B2Replay suspension in a memory systemIBM·Filed 2013·Granted Sep 15, 2015·4 cites·20 claims
- 1777US6785759B1System and method for sharing I/O address translation caching across multiple host bridgesIBM·Filed 2000·Granted Aug 31, 2004·24 cites·23 claims
- 1875US9563548B2Error injection and error counting during memory scrubbing operationsIBM·Filed 2015·Granted Feb 7, 2017·3 cites·7 claims
- 1975US6490660B1Method and apparatus for a configurable multiple level cache with coherency in a multiprocessor systemIBM·Filed 2000·Granted Dec 3, 2002·19 cites·7 claims
- 2071US9459997B2Error injection and error counting during memory scrubbing operationsIBM·Filed 2014·Granted Oct 4, 2016·3 cites·13 claims
- 2170US9092330B2Early data delivery prior to error detection completionIBM·Filed 2013·Granted Jul 28, 2015·2 cites·8 claims
- 2270US5454093ABuffer bypass for quick data accessIBM·Filed 1991·Granted Sep 26, 1995·63 cites·28 claims
- 2368US6115795AMethod and apparatus for configurable multiple level cache with coherency in a multiprocessor systemIBM·Filed 1997·Granted Sep 5, 2000·44 cites·9 claims
- 2467US9037811B2Tagging in memory control unit (MCU)IBM·Filed 2013·Granted May 19, 2015·2 cites·17 claims
- 2567US6973528B2Data caching on bridge following disconnectIBM·Filed 2002·Granted Dec 6, 2005·13 cites·20 claims
- 2666US6065101APipelined snooping of multiple L1 cache linesIBM·Filed 1997·Granted May 16, 2000·41 cites·6 claims
- 2765US11609817B2Low latency availability in degraded redundant array of independent memoryIBM·Filed 2021·Granted Mar 21, 2023·0 cites·20 claims
- 2857US11907074B2Low-latency deserializer having fine granularity and defective-lane compensationIBM·Filed 2021·Granted Feb 20, 2024·0 cites·20 claims
- 2957US9594646B2Reestablishing synchronization in a memory systemIBM·Filed 2016·Granted Mar 14, 2017·0 cites·1 claims
- 3056US9495254B2Synchronization and order detection in a memory systemIBM·Filed 2016·Granted Nov 15, 2016·0 cites·1 claims
- 3155US11520659B2Refresh-hiding memory system staggered refreshIBM·Filed 2020·Granted Dec 6, 2022·0 cites·20 claims
- 3255US9535778B2Reestablishing synchronization in a memory systemIBM·Filed 2013·Granted Jan 3, 2017·0 cites·10 claims
- 3354US10833707B2Error trapping in memory structuresIBM·Filed 2019·Granted Nov 10, 2020·0 cites·18 claims
- 3451US2024103967A1Memory Decoder Providing Optimized Error Detection and Correction for Data Distributed Across Memory ChannelsIBM·Filed 2022·Application pending·0 cites
- 3550US10055287B2Reducing uncorrectable errors based on a history of correctable errorsIBM·Filed 2017·Granted Aug 21, 2018·0 cites·1 claims
- 3648US11960426B2Cable pair concurrent servicingIBM·Filed 2022·Granted Apr 16, 2024·0 cites·14 claims
- 3747US4964737ARemovable thermocouple template for monitoring temperature of multichip modulesIBM·Filed 1989·Granted Oct 23, 1990·13 cites·21 claims
- 3846US10684968B2Conditional memory spreading for heterogeneous memory sizesIBM·Filed 2017·Granted Jun 16, 2020·0 cites·18 claims
- 3944US10254961B2Dynamic load based memory tag managementIBM·Filed 2017·Granted Apr 9, 2019·0 cites·16 claims
- 4043US6438657B1Pipelined snooping of multiple L1 cache linesIBM·Filed 1999·Granted Aug 20, 2002·12 cites·5 claims
- 4140US6138206AData register for multicycle data cache readIBM·Filed 1997·Granted Oct 24, 2000·15 cites·9 claims
- 4238US10601448B2Reduced latency error correction decodingIBM·Filed 2017·Granted Mar 24, 2020·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →