Inventor · disambiguated record
Goran H K Bilski
Also filed as: BILSKI GORAN H K · BILSKI GORAN HK
22 granted patents·1 pending application·98 citations·filing 2018–2024
94Inventor score
Files withXILINX INC23
Top patents by PatentIndex Score
23 records- 0196US10866753B2Data processing engine arrangement in a deviceXILINX INC·Filed 2018·Granted Dec 15, 2020·15 cites·10 claims
- 0296US10747690B2Device with data processing engine arrayXILINX INC·Filed 2018·Granted Aug 18, 2020·19 cites·20 claims
- 0395US11669464B1Multi-addressing mode for DMA and non-sequential read and write patternsXILINX INC·Filed 2020·Granted Jun 6, 2023·9 cites·20 claims
- 0494US11323391B1Multi-port stream switch for stream interconnect networkXILINX INC·Filed 2020·Granted May 3, 2022·6 cites·20 claims
- 0594US10824584B1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2018·Granted Nov 3, 2020·13 cites·20 claims
- 0691US10635622B2System-on-chip interface architectureXILINX INC·Filed 2018·Granted Apr 28, 2020·10 cites·8 claims
- 0785US10990552B1Streaming interconnect architecture for data processing engine arrayXILINX INC·Filed 2018·Granted Apr 27, 2021·4 cites·20 claims
- 0884US11386020B1Programmable device having a data processing engine (DPE) arrayXILINX INC·Filed 2020·Granted Jul 12, 2022·2 cites·21 claims
- 0984US11113223B1Dual mode interconnectXILINX INC·Filed 2018·Granted Sep 7, 2021·4 cites·23 claims
- 1083US11573726B1Data processing engine arrangement in a deviceXILINX INC·Filed 2020·Granted Feb 7, 2023·1 cites·8 claims
- 1182US11016822B1Cascade streaming between data processing engines in an arrayXILINX INC·Filed 2018·Granted May 25, 2021·3 cites·21 claims
- 1282US10747531B1Core for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Aug 18, 2020·3 cites·20 claims
- 1379US11379389B1Communicating between data processing engines using shared memoryXILINX INC·Filed 2018·Granted Jul 5, 2022·2 cites·20 claims
- 1479US2024256482A1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2024·Application pending·0 cites
- 1578US11567881B1Event-based debug, trace, and profile in device with data processing engine arrayXILINX INC·Filed 2018·Granted Jan 31, 2023·2 cites·20 claims
- 1677US12105667B2Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2023·Granted Oct 1, 2024·0 cites·20 claims
- 1777US11972132B2Data processing engine arrangement in a deviceXILINX INC·Filed 2022·Granted Apr 30, 2024·0 cites·19 claims
- 1877US10579559B1Stall logic for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Mar 3, 2020·2 cites·19 claims
- 1975US11061673B1Data selection network for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Jul 13, 2021·2 cites·16 claims
- 2071US11372803B2Data processing engine tile architecture for an integrated circuitXILINX INC·Filed 2018·Granted Jun 28, 2022·1 cites·19 claims
- 2168US11853235B2Communicating between data processing engines using shared memoryXILINX INC·Filed 2022·Granted Dec 26, 2023·0 cites·20 claims
- 2268US11599498B1Device with data processing engine array that enables partial reconfigurationXILINX INC·Filed 2020·Granted Mar 7, 2023·0 cites·20 claims
- 2366US11730325B2Dual mode interconnectXILINX INC·Filed 2021·Granted Aug 22, 2023·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →