Inventor · disambiguated record
Gregg William Baeckler
Also filed as: BAECKLER GREGG · BAECKLER GREGG W · BAECKLER GREGG WILLIAM
95 granted patents·10 pending applications·868 citations·filing 2002–2025
99Inventor score
Top patents by PatentIndex Score
105 records- 0197US10922471B2High performance regularized network-on-chip architectureINTEL CORP·Filed 2019·Granted Feb 16, 2021·19 cites·20 claims
- 0297US7120883B1Register retiming techniqueALTERA CORP·Filed 2003·Granted Oct 10, 2006·129 cites·6 claims
- 0395US9419746B1Apparatus and methods for tuning a communication link for power conservationALTERA CORP·Filed 2014·Granted Aug 16, 2016·30 cites·19 claims
- 0495US9330740B1First-in first-out circuits and methodsALTERA CORP·Filed 2013·Granted May 3, 2016·25 cites·22 claims
- 0594US9053274B1Register retiming techniqueALTERA CORP·Filed 2014·Granted Jun 9, 2015·14 cites·17 claims
- 0694US7689955B1Register retiming techniqueALTERA CORP·Filed 2006·Granted Mar 30, 2010·28 cites·20 claims
- 0794US7538579B1Omnibus logic elementALTERA CORP·Filed 2006·Granted May 26, 2009·22 cites·18 claims
- 0894US7337100B1Physical resynthesis of a logic designALTERA CORP·Filed 2003·Granted Feb 26, 2008·142 cites·39 claims
- 0993US8402408B1Register retiming techniqueVAN ANTWERPEN BABETTE·Filed 2011·Granted Mar 19, 2013·19 cites·20 claims
- 1092US7902864B1Heterogeneous labsALTERA CORP·Filed 2005·Granted Mar 8, 2011·22 cites·45 claims
- 1192US7167022B1Omnibus logic element including look up table based logic elementsALTERA CORP·Filed 2004·Granted Jan 23, 2007·47 cites·22 claims
- 1291US8108812B1Register retiming techniqueVAN ANTWERPEN BABETTE·Filed 2010·Granted Jan 31, 2012·12 cites·20 claims
- 1391US7640528B1Hardware acceleration of functional factoringALTERA CORP·Filed 2006·Granted Dec 29, 2009·23 cites·36 claims
- 1489US8237465B1Omnibus logic element for packing or fracturingSCHLEICHER JAMES·Filed 2011·Granted Aug 7, 2012·9 cites·19 claims
- 1589US7705628B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersALTERA CORP·Filed 2006·Granted Apr 27, 2010·13 cites·24 claims
- 1688US10732932B2Methods for using a multiplier circuit to support multiple sub-multiplications using bit correction and extensionINTEL CORP·Filed 2018·Granted Aug 4, 2020·6 cites·22 claims
- 1788US7877710B1Method and apparatus for deriving signal activities for power analysis and optimizationALTERA CORP·Filed 2006·Granted Jan 25, 2011·14 cites·29 claims
- 1888US7671625B1Omnibus logic elementALTERA CORP·Filed 2008·Granted Mar 2, 2010·10 cites·20 claims
- 1988US7594208B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2006·Granted Sep 22, 2009·18 cites·31 claims
- 2086US11467804B2Geometric synthesisINTEL CORP·Filed 2019·Granted Oct 11, 2022·4 cites·20 claims
- 2186US7911230B1Omnibus logic element for packing or fracturingALTERA CORP·Filed 2009·Granted Mar 22, 2011·8 cites·20 claims
- 2285US9496875B1Omnibus logic elementALTERA CORP·Filed 2014·Granted Nov 15, 2016·4 cites·20 claims
- 2385US8943393B1Distributed burst error protectionMENDEL DAVID W·Filed 2011·Granted Jan 27, 2015·7 cites·20 claims
- 2485US7441212B1State machine recognition and optimizationALTERA CORP·Filed 2005·Granted Oct 21, 2008·16 cites·36 claims
- 2585US7268584B1Adder circuitry for a programmable logic deviceALTERA CORP·Filed 2005·Granted Sep 11, 2007·15 cites·27 claims
- 2684US10177766B1Omnibus logic elementALTERA CORP·Filed 2016·Granted Jan 8, 2019·2 cites·15 claims
- 2784US9230047B1Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvementVAN ANTWERPEN BABETTE·Filed 2010·Granted Jan 5, 2016·9 cites·26 claims
- 2884US7565388B1Logic cell supporting addition of three binary wordsALTERA CORP·Filed 2003·Granted Jul 21, 2009·36 cites·26 claims
- 2983US8806399B1Register retiming techniqueALTERA CORP·Filed 2013·Granted Aug 12, 2014·4 cites·20 claims
- 3083US7386828B1SAT-based technology mapping frameworkALTERA CORP·Filed 2006·Granted Jun 10, 2008·13 cites·20 claims
- 3182US8878567B1Omnibus logic elementALTERA CORP·Filed 2013·Granted Nov 4, 2014·3 cites·15 claims
- 3281US12206410B2Programmable logic device with fine-grained disaggregationINTEL CORP·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 3381US10601426B1Programmable logic device with fine-grained disaggregationINTEL CORP·Filed 2018·Granted Mar 24, 2020·2 cites·21 claims
- 3480US9048889B1High-speed data communications architectureALTERA CORP·Filed 2013·Granted Jun 2, 2015·5 cites·24 claims
- 3580US8593174B1Omnibus logic element for packing or fracturingSCHLEICHER JAMES·Filed 2012·Granted Nov 26, 2013·3 cites·20 claims
- 3679US10715144B2Logic circuits with augmented arithmetic densitiesINTEL CORP·Filed 2019·Granted Jul 14, 2020·2 cites·20 claims
- 3778US8479143B1Signature based duplicate extractionBAECKLER GREGG WILLIAM·Filed 2010·Granted Jul 2, 2013·5 cites·23 claims
- 3877US9203604B1Methods and apparatus for performing bit swapping in clock data recovery circuitryALTERA CORP·Filed 2013·Granted Dec 1, 2015·4 cites·20 claims
- 3977US8661380B1Method and apparatus for performing parallel synthesis on a field programmable gate arrayBAECKLER GREGG WILLIAM·Filed 2008·Granted Feb 25, 2014·7 cites·37 claims
- 4077US7181703B1Techniques for automated sweeping of parameters in computer-aided design to achieve optimum performance and resource usageALTERA CORP·Filed 2003·Granted Feb 20, 2007·22 cites·21 claims
- 4176US9490836B2Apparatus for improved encoding and associated methodsALTERA CORP·Filed 2012·Granted Nov 8, 2016·5 cites·24 claims
- 4276US8756540B1Method and apparatus for extracted synthesis gate characteristics modelBAECKLER GREGG WILLIAM·Filed 2008·Granted Jun 17, 2014·13 cites·46 claims
- 4376US2024394448A1Programmable integrated circuit underlayINTEL CORP·Filed 2024·Application pending·0 cites
- 4474US11595045B2Programmable logic device with fine-grained disaggregationINTEL CORP·Filed 2021·Granted Feb 28, 2023·0 cites·20 claims
- 4573US9417984B1Preemptively generating statistical feedback on a design file and presenting the feedback in an input contextALTERA CORP·Filed 2013·Granted Aug 16, 2016·5 cites·21 claims
- 4673US9304899B1Network interface circuitry with flexible memory addressing capabilitiesBAECKLER GREGG WILLIAM·Filed 2012·Granted Apr 5, 2016·3 cites·23 claims
- 4773US7890910B1Programmable logic device having logic elements with dedicated hardware to configure look up tables as registersALTERA CORP·Filed 2006·Granted Feb 15, 2011·5 cites·20 claims
- 4873US2025199762A1Machine learning training architecture for programmable devicesALTERA CORP·Filed 2025·Application pending·0 cites
- 4972US2025238232A1Vector Processor ArchitecturesALTERA CORP·Filed 2025·Application pending·0 cites
- 5071US11070209B2Programmable logic device with fine-grained disaggregationINTEL CORP·Filed 2020·Granted Jul 20, 2021·0 cites·7 claims
Showing the top 50 of 105 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →