Inventor · disambiguated record
Gregory Christopher Burda
Also filed as: BURDA GREGORY CHRISTOPHER
10 granted patents·2 pending applications·196 citations·filing 2000–2023
89Inventor score
Files withQUALCOMM INC5BURDA GREGORY CHRISTOPHER2IBM2MICROSOFT TECHNOLOGY LICENSING LLC2PUCKETT JOSHUA L1
Top patents by PatentIndex Score
12 records- 0195US9070551B2Method and apparatus for a diffusion bridged cell libraryQUALCOMM INC·Filed 2013·Granted Jun 30, 2015·60 cites·7 claims
- 0295US8782576B1Method and apparatus for a diffusion bridged cell libraryQUALCOMM INC·Filed 2013·Granted Jul 15, 2014·73 cites·2 claims
- 0391US8578117B2Write-through-read (WTR) comparator circuits, systems, and methods use of same with a multiple-port fileBURDA GREGORY CHRISTOPHER·Filed 2010·Granted Nov 5, 2013·37 cites·22 claims
- 0474US7242624B2Methods and apparatus for reading a full-swing memory arrayQUALCOMM INC·Filed 2005·Granted Jul 10, 2007·9 cites·13 claims
- 0569US7698536B2Method and system for providing an energy efficient register fileQUALCOMM INC·Filed 2005·Granted Apr 13, 2010·4 cites·21 claims
- 0664US12057159B2Memory system with burst mode having logic gates as sense elementsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2023·Granted Aug 6, 2024·0 cites·20 claims
- 0757US11699483B2Memory system with burst mode having logic gates as sense elementsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Jul 11, 2023·0 cites·20 claims
- 0857US6735145B1Method and circuit for optimizing power consumption and performance of driver circuitsIBM·Filed 2002·Granted May 11, 2004·9 cites·6 claims
- 0954US2015064864A1Method and apparatus for a diffusion bridged cell libraryQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1048US8315078B2Power saving static-based comparator circuits and methods and content-addressable memory (CAM) circuits employing sameBURDA GREGORY CHRISTOPHER·Filed 2009·Granted Nov 20, 2012·2 cites·15 claims
- 1146US6320419B1Non-latency affected contention prevention during scan-based testIBM·Filed 2000·Granted Nov 20, 2001·2 cites·11 claims
- 1234US2013185527A1Asymmetrically-Arranged Memories having Reduced Current Leakage and/or Latency, and Related Systems and MethodsPUCKETT JOSHUA L·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →