Inventor · disambiguated record
Guilhem Bouton
Also filed as: BOUTON GUILHEM
21 granted patents·2 pending applications·21 citations·filing 2003–2021
91Inventor score
Files withST MICROELECTRONICS ROUSSET18BOUTON GUILHEM2STMICROELECTRONICS ROUSSET2ST MICROELECTRONICS SA1
Top patents by PatentIndex Score
23 records- 0193US9269771B2Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stressesST MICROELECTRONICS ROUSSET·Filed 2015·Granted Feb 23, 2016·8 cites·15 claims
- 0287US9263518B2Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication methodST MICROELECTRONICS ROUSSET·Filed 2014·Granted Feb 16, 2016·7 cites·14 claims
- 0383US11244893B2Low-dispersion component in an electronic chipST MICROELECTRONICS ROUSSET·Filed 2018·Granted Feb 8, 2022·2 cites·18 claims
- 0482US10043741B2Low-dispersion component in an electronic chipST MICROELECTRONICS ROUSSET·Filed 2016·Granted Aug 7, 2018·2 cites·16 claims
- 0574US12087683B2Low-dispersion component in an electronic chipST MICROELECTRONICS ROUSSET·Filed 2021·Granted Sep 10, 2024·0 cites·12 claims
- 0671US10714583B2MOS transistor with reduced hump effectST MICROELECTRONICS ROUSSET·Filed 2018·Granted Jul 14, 2020·1 cites·49 claims
- 0764US10770547B2Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stressesST MICROELECTRONICS ROUSSET·Filed 2019·Granted Sep 8, 2020·0 cites·8 claims
- 0862US10490632B2Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stressesST MICROELECTRONICS ROUSSET·Filed 2019·Granted Nov 26, 2019·0 cites·6 claims
- 0959US10861802B2Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuitST MICROELECTRONICS ROUSSET·Filed 2018·Granted Dec 8, 2020·0 cites·17 claims
- 1059US10211291B2Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stressesST MICROELECTRONICS ROUSSET·Filed 2018·Granted Feb 19, 2019·0 cites·17 claims
- 1155US9899476B2Integrated circuit comprising components, for example NMOS transistors, having active regions with relaxed compressive stressesST MICROELECTRONICS ROUSSET·Filed 2015·Granted Feb 20, 2018·0 cites·15 claims
- 1254US10177101B2Method for forming at least one electrical discontinuity in an integrated circuit, and corresponding integrated circuitST MICROELECTRONICS ROUSSET·Filed 2017·Granted Jan 8, 2019·0 cites·10 claims
- 1354US9780045B2Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuitSTMICROELECTRONICS ROUSSET·Filed 2017·Granted Oct 3, 2017·0 cites·22 claims
- 1450US9640493B2Method for fabrication of an integrated circuit rendering a reverse engineering of the integrated circuit more difficult and corresponding integrated circuitSTMICROELECTRONICS ROUSSET·Filed 2015·Granted May 2, 2017·0 cites·27 claims
- 1546US10049991B2Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit, and corresponding integrated circuitST MICROELECTRONICS ROUSSET·Filed 2017·Granted Aug 14, 2018·0 cites·10 claims
- 1645US10115666B2Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding theretoST MICROELECTRONICS ROUSSET·Filed 2014·Granted Oct 30, 2018·0 cites·20 claims
- 1745US6780716B2Chip differentiation at the level of a reticleST MICROELECTRONICS SA·Filed 2003·Granted Aug 24, 2004·1 cites·10 claims
- 1845US2015255540A1Component, for example nmos transistor, with active region with relaxed compression stresses, and fabrication methodST MICROELECTRONICS ROUSSET·Filed 2015·Application pending·0 cites
- 1943US10049982B2Method for forming at least one electrical discontinuity in an interconnection part of an integrated circuit without addition of additional material, and corresponding integrated circuitST MICROELECTRONICS ROUSSET·Filed 2017·Granted Aug 14, 2018·0 cites·11 claims
- 2040US10418322B2Method for making a photolithography mask intended for the formation of contacts, mask and integrated circuit corresponding theretoST MICROELECTRONICS ROUSSET·Filed 2015·Granted Sep 17, 2019·0 cites·21 claims
- 2138US8914756B2Process for fabricating an integrated circuit comprising an analog block and a digital block, and corresponding integrated circuitBOUTON GUILHEM·Filed 2011·Granted Dec 16, 2014·0 cites·8 claims
- 2237US8881090B2Method for fabrication of an integrated circuit in a technology reduced with respect to a native technology, and corresponding integrated circuitBOUTON GUILHEM·Filed 2012·Granted Nov 4, 2014·0 cites·9 claims
- 2333US2015340426A1Component, for example nmos transistor, with an active region under relaxed compressive stress, and associated decoupling capacitorST MICROELECTRONICS ROUSSET·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →