Inventor · disambiguated record
Guy Dupenloup
Also filed as: DUPENLOUP GUY
15 granted patents·1,212 citations·filing 1998–2012
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
15 records- 0193US6836877B1Automatic synthesis script generation for synopsys design compilerLSI LOGIC CORP·Filed 1998·Granted Dec 28, 2004·244 cites·18 claims
- 0288US6421818B1Efficient top-down characterization methodLSI LOGIC CORP·Filed 1998·Granted Jul 16, 2002·152 cites·15 claims
- 0388US6378123B1Method of handling macro components in circuit design synthesisLSI LOGIC CORP·Filed 1998·Granted Apr 23, 2002·149 cites·11 claims
- 0486US6295636B1RTL analysis for improved logic synthesisLSI LOGIC CORP·Filed 1998·Granted Sep 25, 2001·134 cites·14 claims
- 0585US6292931B1RTL analysis toolLSI LOGIC CORP·Filed 1998·Granted Sep 18, 2001·124 cites·35 claims
- 0684US6173435B1Internal clock handling in synthesis scriptLSI LOGIC CORP·Filed 1998·Granted Jan 9, 2001·110 cites·10 claims
- 0778US8095899B1Verifiable multimode multipliersDUPENLOUP GUY·Filed 2009·Granted Jan 10, 2012·7 cites·6 claims
- 0878US6205572B1Buffering tree analysis in mapped designLSI LOGIC CORP·Filed 1998·Granted Mar 20, 2001·82 cites·19 claims
- 0977US6289498B1VDHL/Verilog expertise and gate synthesis automation systemLSI LOGIC CORP·Filed 1998·Granted Sep 11, 2001·77 cites·12 claims
- 1077US6263483B1Method of accessing the generic netlist created by synopsys design compilierLSI LOGIC CORP·Filed 1998·Granted Jul 17, 2001·77 cites·27 claims
- 1174US8336007B1Verifiable multimode multipliersDUPENLOUP GUY·Filed 2012·Granted Dec 18, 2012·3 cites·23 claims
- 1266US7506017B1Verifiable multimode multipliersALTERA CORP·Filed 2004·Granted Mar 17, 2009·9 cites·16 claims
- 1362US6289491B1Netlist analysis tool by degree of conformityLSI LOGIC CORP·Filed 1998·Granted Sep 11, 2001·40 cites·17 claims
- 1450US7178117B1Apparatus and method for RTL based full chip modeling of a programmable logic deviceALTERA CORP·Filed 2004·Granted Feb 13, 2007·4 cites·15 claims
- 1541US7308659B1Apparatus and method for RTL modeling of a registerALTERA CORP·Filed 2003·Granted Dec 11, 2007·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →