Inventor · disambiguated record
Guenter Mayer
Also filed as: MAYER GUENTER
7 granted patents·4 pending applications·62 citations·filing 1994–2015
83Inventor score
Files withIBM7BOSCH GMBH ROBERT1GELLERICH WOLFGANG1HALLER WILHELM1Rheinische Friedrich-Wilhelms-Universität Bonn1
Top patents by PatentIndex Score
11 records- 0163US5588465AValve blockBOSCH GMBH ROBERT·Filed 1994·Granted Dec 31, 1996·32 cites·8 claims
- 0260US6341093B1SOI array sense and write margin qualificationIBM·Filed 2001·Granted Jan 22, 2002·11 cites·13 claims
- 0357US7755394B2Circuit combining level shift function with gated resetIBM·Filed 2008·Granted Jul 13, 2010·3 cites·1 claims
- 0456US8612500B2Method and decimal arithmetic logic unit structure to generate a magnitude result of a mathematicHALLER WILHELM·Filed 2008·Granted Dec 17, 2013·2 cites·14 claims
- 0556US8001411B2Generating a local clock domain using dynamic controlsIBM·Filed 2007·Granted Aug 16, 2011·3 cites·20 claims
- 0656US6930902B2Device for storing information and a method for partial write and restoreIBM·Filed 2003·Granted Aug 16, 2005·9 cites·22 claims
- 0744US2008071852A1Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a methodIBM·Filed 2007·Application pending·0 cites
- 0844US2009112963A1Method to perform a subtraction of two operands in a binary arithmetic unit plus arithmetic unit to perform such a methodIBM·Filed 2007·Application pending·0 cites
- 0942US6614265B2Static logic compatible multiport latchIBM·Filed 2001·Granted Sep 2, 2003·2 cites·11 claims
- 1040US2013096901A1Verifying Simulation Design ModificationsGELLERICH WOLFGANG·Filed 2011·Application pending·0 cites
- 1134US2017298343A1Method of identifying or producing an aptamerRHEINISCHE FRIEDRICH-WILHELMS UNIVERSITÄT BONN·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →