Inventor · disambiguated record
Gurushankar Rajamani
Also filed as: RAJAMANI GURUSHANKAR
17 granted patents·3 pending applications·56 citations·filing 1999–2024
89Inventor score
Top patents by PatentIndex Score
20 records- 0193US11934826B2Vector reductions using shared scratchpad memoryGOOGLE LLC·Filed 2021·Granted Mar 19, 2024·3 cites·8 claims
- 0287US11182159B2Vector reductions using shared scratchpad memoryGOOGLE LLC·Filed 2020·Granted Nov 23, 2021·2 cites·25 claims
- 0380US11295206B2Interleaving memory requests to accelerate memory accessesGOOGLE LLC·Filed 2020·Granted Apr 5, 2022·2 cites·20 claims
- 0478US6810372B1Multimodal optimization technique in test generationHEWLETT PACKARD DEVELOPMENT CO·Filed 1999·Granted Oct 26, 2004·44 cites·12 claims
- 0570US11748028B2Data processing on memory controllerGOOGLE LLC·Filed 2022·Granted Sep 5, 2023·0 cites·20 claims
- 0668US2025103426A1Memory Sparing to Improve Chip ReliabilityGOOGLE LLC·Filed 2024·Application pending·0 cites
- 0766US7770051B2Strategy to verify asynchronous links across chipsINTEL CORP·Filed 2008·Granted Aug 3, 2010·2 cites·19 claims
- 0865US11513724B2Data processing on memory controllerGOOGLE LLC·Filed 2021·Granted Nov 29, 2022·0 cites·21 claims
- 0964US12353340B2Systems for high-speed computing using an optical interchangeGOOGLE LLC·Filed 2023·Granted Jul 8, 2025·0 cites·20 claims
- 1063US12242338B2Memory sparing to improve chip reliabilityGOOGLE LLC·Filed 2023·Granted Mar 4, 2025·0 cites·16 claims
- 1162US11928580B2Interleaving memory requests to accelerate memory accessesGOOGLE LLC·Filed 2022·Granted Mar 12, 2024·0 cites·20 claims
- 1261US11137936B2Data processing on memory controllerGOOGLE LLC·Filed 2020·Granted Oct 5, 2021·0 cites·20 claims
- 1357US2025045238A1Systems and Methods For High Bandwidth Memory With Unidirectional Data FlowGOOGLE LLC·Filed 2024·Application pending·0 cites
- 1456US12132802B2Off-chip memory backed reliable transport connection cache hardware architectureGOOGLE LLC·Filed 2021·Granted Oct 29, 2024·0 cites·20 claims
- 1556US7464287B2Strategy to verify asynchronous links across chipsINTEL CORP·Filed 2004·Granted Dec 9, 2008·3 cites·29 claims
- 1650US9594713B2Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable mediaQUALCOMM INC·Filed 2014·Granted Mar 14, 2017·0 cites·20 claims
- 1744US8209563B2Strategy to verify asynchronous links across chipsSHARMA DEBENDRA DAS·Filed 2010·Granted Jun 26, 2012·0 cites·19 claims
- 1841US2004078712A1Method and apparatus for stressing data pathsFiled 2002·Application pending·0 cites
- 1940US8782318B2Increasing Input Output Hubs in constrained link based multi-processor systemsSHARMA DEBENDRA DAS·Filed 2011·Granted Jul 15, 2014·0 cites·20 claims
- 2038US9164943B2Self correction logic for serial-to-parallel convertersSHARMA ANIL·Filed 2012·Granted Oct 20, 2015·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →