Inventor · disambiguated record
Guenter Stenz
Also filed as: STENZ GUENTER
20 granted patents·391 citations·filing 2002–2021
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
20 records- 0196US6789244B1Placement of clock objects under constraintsXILINX INC·Filed 2002·Granted Sep 7, 2004·178 cites·20 claims
- 0293US7143380B1Method for application of network flow techniques under constraintsXILINX INC·Filed 2002·Granted Nov 28, 2006·97 cites·44 claims
- 0385US10891413B1Incremental initialization by parent and child placer processes in processing a circuit designXILINX INC·Filed 2019·Granted Jan 12, 2021·5 cites·20 claims
- 0484US11003827B1Multiprocessing flow and massively multi-threaded flow for multi-die devicesXILINX INC·Filed 2020·Granted May 11, 2021·3 cites·20 claims
- 0583US11875100B1Distributed parallel processing routingXILINX INC·Filed 2021·Granted Jan 16, 2024·2 cites·20 claims
- 0683US7958480B1Placement of I/O blocks within I/O banks using an integer linear programming formulationXILINX INC·Filed 2008·Granted Jun 7, 2011·14 cites·20 claims
- 0776US8312405B1Method of placing input/output blocks on an integrated circuit deviceSLONIM VICTOR·Filed 2009·Granted Nov 13, 2012·11 cites·20 claims
- 0874US9881112B1Vectorless dynamic power estimation for sequential circuitsXILINX INC·Filed 2015·Granted Jan 30, 2018·2 cites·20 claims
- 0973US7512922B1Methods of structured placement of a circuit designXILINX INC·Filed 2007·Granted Mar 31, 2009·6 cites·20 claims
- 1072US8082532B1Placing complex function blocks on a programmable integrated circuitSTENZ GUENTER·Filed 2009·Granted Dec 20, 2011·9 cites·20 claims
- 1171US10416232B1Timing optimizations in circuit designs using opposite clock edge triggered flip-flopsXILINX INC·Filed 2018·Granted Sep 17, 2019·1 cites·20 claims
- 1270US8010924B1Assignment of select input/output blocks to banks for integrated circuits using integer linear programming with proximity optimizationXILINX INC·Filed 2008·Granted Aug 30, 2011·5 cites·20 claims
- 1370US6857115B1Placement of objects with partial shape restrictionXILINX INC·Filed 2002·Granted Feb 15, 2005·15 cites·26 claims
- 1468US7072815B1Relocation of components for post-placement optimizationXILINX INC·Filed 2002·Granted Jul 4, 2006·14 cites·24 claims
- 1567US7392499B1Placement of input/output blocks of an electronic design in an integrated circuitXILINX INC·Filed 2005·Granted Jun 24, 2008·4 cites·20 claims
- 1660US7313778B1Method system and apparatus for floorplanning programmable logic designsXILINX INC·Filed 2004·Granted Dec 25, 2007·8 cites·27 claims
- 1759US7149993B1Method, system, and apparatus for incremental design in programmable logic devices using floorplanningXILINX INC·Filed 2004·Granted Dec 12, 2006·7 cites·20 claims
- 1857US6983439B1Unified placer infrastructureXILINX INC·Filed 2002·Granted Jan 3, 2006·5 cites·8 claims
- 1956US6957406B1Analytical placement methods with minimum preplaced componentsXILINX INC·Filed 2002·Granted Oct 18, 2005·5 cites·7 claims
- 2051US11106851B1Serialization in electronic design automation flowsXILINX INC·Filed 2020·Granted Aug 31, 2021·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →