Inventor · disambiguated record
Han-Pin Chung
Also filed as: CHUNG HAN-PIN
15 granted patents·2 pending applications·73 citations·filing 2010–2023
91Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD7TAIWAN SEMICONDUCTOR MFG6CHUNG HAN-PIN1HUANG YU-LIEN1TSAI CHUN HSIUNG1
Top patents by PatentIndex Score
17 records- 0193US8609497B2Method of dual EPI process for semiconductor deviceCHUNG HAN-PIN·Filed 2010·Granted Dec 17, 2013·28 cites·20 claims
- 0289US9362404B2Doping for FinFETTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Jun 7, 2016·8 cites·18 claims
- 0389US9218974B2Sidewall free CESL for enlarging ILD gap-fill windowTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 22, 2015·8 cites·20 claims
- 0487US10840154B2Method for forming semiconductor structure with high aspect ratioTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Nov 17, 2020·3 cites·20 claims
- 0587US8900957B2Method of dual epi process for semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 2, 2014·7 cites·12 claims
- 0685US11823960B2Method for forming semiconductor structure with high aspect ratioTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 21, 2023·1 cites·20 claims
- 0783US12369390B2Method for forming semiconductor structure with high aspect ratioTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 22, 2025·0 cites·20 claims
- 0883US8900956B2Method of dual EPI process for semiconductor deviceTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 2, 2014·5 cites·20 claims
- 0982US8461015B2STI structure and method of forming bottom void in sameHUANG YU-LIEN·Filed 2010·Granted Jun 11, 2013·7 cites·20 claims
- 1081US10872961B2Semiconductor device and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 22, 2020·3 cites·20 claims
- 1178US9659776B2Doping for FinFETTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 23, 2017·2 cites·20 claims
- 1264US8999834B2Sidewall-free CESL for enlarging ILD gap-fill windowTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 7, 2015·1 cites·20 claims
- 1347US12444601B2Semiconductor device and method of forming thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Oct 14, 2025·0 cites·20 claims
- 1445US2010314690A1Sidewall-Free CESL for Enlarging ILD Gap-Fill WindowTAIWAN SEMICONDUCTOR MFG·Filed 2010·Application pending·0 cites
- 1544US10629497B2FinFET device structure and method for enlarging gap-fill windowTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Apr 21, 2020·0 cites·20 claims
- 1641US8569185B2Method of fabricating gate electrode using a treated hard maskYEH MATT·Filed 2010·Granted Oct 29, 2013·0 cites·20 claims
- 1737US2012015459A1Thermal Leveling for Semiconductor DevicesTSAI CHUN HSIUNG·Filed 2010·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →