Inventor · disambiguated record
Harald D. Folberth
Also filed as: FOLBERTH HARALD · FOLBERTH HARALD D
21 granted patents·2 pending applications·48 citations·filing 1997–2019
92Inventor score
Files withIBM23
Top patents by PatentIndex Score
23 records- 0186US9928329B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2016·Granted Mar 27, 2018·3 cites·20 claims
- 0286US9910948B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2016·Granted Mar 6, 2018·3 cites·16 claims
- 0384US10242140B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2017·Granted Mar 26, 2019·2 cites·18 claims
- 0484US10235487B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2017·Granted Mar 19, 2019·2 cites·9 claims
- 0580US11080456B2Automated design closure with abutted hierarchyIBM·Filed 2019·Granted Aug 3, 2021·4 cites·17 claims
- 0675US10223489B2Placement clustering-based white space reservationIBM·Filed 2016·Granted Mar 5, 2019·2 cites·20 claims
- 0775US9536037B2Circuit placement with electro-migration mitigationIBM·Filed 2015·Granted Jan 3, 2017·2 cites·13 claims
- 0872US9384316B2Path-based congestion reduction in integrated circuit routingIBM·Filed 2014·Granted Jul 5, 2016·3 cites·17 claims
- 0968US9471741B1Circuit routing based on total negative slackIBM·Filed 2015·Granted Oct 18, 2016·1 cites·7 claims
- 1067US10534884B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2019·Granted Jan 14, 2020·0 cites·20 claims
- 1165US10616103B2Constructing staging trees in hierarchical circuit designsIBM·Filed 2017·Granted Apr 7, 2020·1 cites·20 claims
- 1265US10417366B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2018·Granted Sep 17, 2019·0 cites·20 claims
- 1365US10366191B2Layout of large block synthesis blocks in integrated circuitsIBM·Filed 2018·Granted Jul 30, 2019·0 cites·11 claims
- 1456US10169519B2Area sharing between multiple large block synthesis (LBS) blocksIBM·Filed 2018·Granted Jan 1, 2019·0 cites·17 claims
- 1552US9946830B2Area sharing between multiple large block synthesis (LBS) blocksIBM·Filed 2016·Granted Apr 17, 2018·0 cites·20 claims
- 1652US9483601B2Circuit routing based on total negative slackIBM·Filed 2015·Granted Nov 1, 2016·0 cites·13 claims
- 1751US9679101B2Circuit placement with electro-migration mitigationIBM·Filed 2015·Granted Jun 13, 2017·0 cites·7 claims
- 1847US6237128B1Method and apparatus for enabling parallel layout checking of designing VLSI-chipsIBM·Filed 1997·Granted May 22, 2001·22 cites·16 claims
- 1944US10831965B1Placement of vectorized latches in hierarchical integrated circuit developmentIBM·Filed 2019·Granted Nov 10, 2020·0 cites·14 claims
- 2042US10146899B1Clock control treesIBM·Filed 2017·Granted Dec 4, 2018·0 cites·20 claims
- 2140US2020210545A1Construction of staging trees on fully hierarchical vlsi circuit designsIBM·Filed 2019·Application pending·0 cites
- 2238US2011109378A1Method and Device For Supplying Power to a Microelectronic ChipIBM·Filed 2010·Application pending·0 cites
- 2327US6043436AWiring structure having rotated wiring layersIBM·Filed 1997·Granted Mar 28, 2000·3 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →