Inventor · disambiguated record
Hans-Oliver Joachim
Also filed as: JOACHIM HANS-OLIVER
21 granted patents·4 pending applications·465 citations·filing 1995–2003
96Inventor score
Top patents by PatentIndex Score
25 records- 0194US5641980ADevice having a high concentration region under the channelMITSUBISHI ELECTRIC CORP·Filed 1995·Granted Jun 24, 1997·127 cites·7 claims
- 0285US6265742B1Memory cell structure and fabricationSIEMENS AG·Filed 1999·Granted Jul 24, 2001·51 cites·12 claims
- 0381US6236617B1High performance CMOS word-line driverIBM·Filed 1999·Granted May 22, 2001·48 cites·16 claims
- 0478US6093614AMemory cell structure and fabricationSIEMENS AG·Filed 1998·Granted Jul 25, 2000·38 cites·7 claims
- 0574US5926703ALDD device having a high concentration region under the channelMITSUBISHI ELECTRIC CORP·Filed 1997·Granted Jul 20, 1999·32 cites·7 claims
- 0671US6323103B1Method for fabricating transistorsSIEMENS AG·Filed 1998·Granted Nov 27, 2001·39 cites·41 claims
- 0769US6687150B1Reference voltage generation for memory circuitsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Feb 3, 2004·20 cites·27 claims
- 0865US6323532B1Deep divot mask for enhanced buried-channel PFET performance and reliabilityIBM·Filed 2000·Granted Nov 27, 2001·13 cites·9 claims
- 0962US6972983B2Increasing the read signal in ferroelectric memoriesINFINEON TECHNOLOGIES AG·Filed 2002·Granted Dec 6, 2005·12 cites·32 claims
- 1062US6826099B22T2C signal margin test mode using a defined charge and discharge of BL and /BLINFINEON TECHNOLOGIES AG·Filed 2002·Granted Nov 30, 2004·12 cites·11 claims
- 1162US6127215ADeep pivot mask for enhanced buried-channel PFET performance and reliabilityIBM·Filed 1998·Granted Oct 3, 2000·23 cites·20 claims
- 1259US6999887B2Memory cell signal window testing apparatusINFINEON TECHNOLOGIES AG·Filed 2003·Granted Feb 14, 2006·10 cites·6 claims
- 1359US6584009B1Memory integrated circuit with improved reliabilityINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 24, 2003·10 cites·15 claims
- 1448US6876590B22T2C signal margin test mode using a defined charge exchange between BL and/BLINFINEON TECHNOLOGIES AG·Filed 2002·Granted Apr 5, 2005·6 cites·11 claims
- 1546US6707699B1Historical information storage for integrated circuitsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Mar 16, 2004·4 cites·19 claims
- 1645US6856560B2Redundancy in series grouped memory architectureINFINEON TECHNOLOGIES AG·Filed 2002·Granted Feb 15, 2005·4 cites·25 claims
- 1744US6885597B2Sensing test circuitTOSHIBA KK·Filed 2002·Granted Apr 26, 2005·4 cites·39 claims
- 1843US2005050261A1High density flash memory with high speed cache data interfaceFiled 2003·Application pending·0 cites
- 1942US6906969B2Hybrid fuses for redundancyTOSHIBA KK·Filed 2002·Granted Jun 14, 2005·3 cites·43 claims
- 2042US6807084B1FeRAM memory deviceINFINEON TECHNOLOGIES AG·Filed 2003·Granted Oct 19, 2004·3 cites·9 claims
- 2140US6903959B2Sensing of memory integrated circuitsINFINEON TECHNOLOGIES AG·Filed 2002·Granted Jun 7, 2005·2 cites·22 claims
- 2239US7102908B2Reliable ferro fuse cellINFINEON TECHNOLOGIES AG·Filed 2003·Granted Sep 5, 2006·4 cites·9 claims
- 2332US2005063212A1Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devicesFiled 2003·Application pending·0 cites
- 2432US2005063213A1Signal margin test mode for FeRAM with ferroelectric reference capacitorFiled 2003·Application pending·0 cites
- 2532US2004095799A12T2C signal margin test mode using different pre-charge levels for BL and/BLFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →