Inventor · disambiguated record
Han-Chao Lai
Also filed as: LAI HAN C · LAI HAN-CHAO
18 granted patents·8 pending applications·347 citations·filing 2001–2020
94Inventor score
Top patents by PatentIndex Score
26 records- 0194US6498377B1SONOS component having high dielectric propertyMACRONIX INT CO LTD·Filed 2002·Granted Dec 24, 2002·107 cites·18 claims
- 0292US6524913B1Method of fabricating a non-volatile memory with a spacerMACRONIX INT CO LTD·Filed 2001·Granted Feb 25, 2003·74 cites·20 claims
- 0382US6720614B2Operation method for programming and erasing a data in a P-channel sonos memory cellMACRONIX INT CO LTD·Filed 2001·Granted Apr 13, 2004·31 cites·12 claims
- 0482US6671209B2Erasing method for p-channel NROMMACRONIX INT CO LTD·Filed 2001·Granted Dec 30, 2003·28 cites·6 claims
- 0575US7132350B2Method for manufacturing a programmable eraseless memoryMACRONIX INT CO LTD·Filed 2003·Granted Nov 7, 2006·13 cites·31 claims
- 0674US7180123B2Method for programming programmable eraseless memoryMACRONIX INT CO LTD·Filed 2003·Granted Feb 20, 2007·19 cites·56 claims
- 0773US6455388B1Method of manufacturing metal-oxide semiconductor transistorMACRONIX INT CO LTD·Filed 2002·Granted Sep 24, 2002·16 cites·13 claims
- 0870US6620693B2Non-volatile memory and fabrication thereofMACRONIX INT CO LTD·Filed 2002·Granted Sep 16, 2003·10 cites·7 claims
- 0969US6635946B2Semiconductor device with trench isolation structureMACRONIX INT CO LTD·Filed 2001·Granted Oct 21, 2003·15 cites·20 claims
- 1060US6458643B1Method of fabricating a MOS device with an ultra-shallow junctionMACRONIX INT CO LTD·Filed 2001·Granted Oct 1, 2002·7 cites·15 claims
- 1159US6555844B1Semiconductor device with minimal short-channel effects and low bit-line resistanceMACRONIX INT CO LTD·Filed 2002·Granted Apr 29, 2003·7 cites·19 claims
- 1257US6448142B1Method for fabricating a metal oxide semiconductor transistorMACRONIX INT CO LTD·Filed 2001·Granted Sep 10, 2002·5 cites·10 claims
- 1356US6524919B2Method for manufacturing a metal oxide semiconductor with a sharp corner spacerMACRONIX INT CO LTD·Filed 2001·Granted Feb 25, 2003·5 cites·19 claims
- 1455US6482709B1Manufacturing process of a MOS transistorMACRONIX INT CO LTD·Filed 2001·Granted Nov 19, 2002·6 cites·9 claims
- 1552US6808995B2Semiconductor device with minimal short-channel effects and low bit-line resistanceMACRONIX INT CO LTD·Filed 2003·Granted Oct 26, 2004·4 cites·11 claims
- 1648US11362099B2Non-volatile memory device and manufacturing method thereofPOWERCHIP SEMICONDUCTOR MFG CORP·Filed 2020·Granted Jun 14, 2022·0 cites·28 claims
- 1747US8501591B2Method for manufacturing a multiple-bit-per-cell memoryYEH CHIH CHIEH·Filed 2005·Granted Aug 6, 2013·0 cites·19 claims
- 1837US2005190601A1Programmable resistor eraseless memoryMACRONIX INT CO LTD·Filed 2005·Application pending·0 cites
- 1936US2003134477A1Memory structure and method for manufacturing the sameFiled 2002·Application pending·0 cites
- 2036US2003132488A1Non-volatile memory and fabrication thereofFiled 2002·Application pending·0 cites
- 2135US2005035429A1Programmable eraseless memoryFiled 2003·Application pending·0 cites
- 2234US6492235B2Method for forming extension by using double etch spacerMACRONIX INT CO LTD·Filed 2001·Granted Dec 10, 2002·0 cites·15 claims
- 2334US2002197780A1Method for forming a metal oxide semiconductor type field effect transistorMACRONIX INT CO LTD·Filed 2001·Application pending·0 cites
- 2434US2004105313A1Erasing method for p-channel NROMFiled 2003·Application pending·0 cites
- 2533US2002086473A1Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effectsFiled 2001·Application pending·0 cites
- 2633US2002155686A1Fabrication method for suppressing a hot carrier effect and leakage currents of I/O devicesFiled 2001·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Han-Chao Lai files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →