Inventor · disambiguated record
Haoxing Ren
Also filed as: REN HAOXING
44 granted patents·16 pending applications·263 citations·filing 2002–2025
97Inventor score
Top patents by PatentIndex Score
60 records- 0196US9501603B2Integrated circuit design changes using through-silicon viasIBM·Filed 2014·Granted Nov 22, 2016·40 cites·10 claims
- 0294US9405866B1Automating a microarchitecture design exploration environmentIBM·Filed 2015·Granted Aug 2, 2016·13 cites·15 claims
- 0393US8271920B2Converged large block and structured synthesis for high performance microprocessor designsCHO MINSIK·Filed 2010·Granted Sep 18, 2012·34 cites·22 claims
- 0491US10657306B1Deep learning testability analysis with graph convolutional networksNVIDIA CORP·Filed 2019·Granted May 19, 2020·13 cites·20 claims
- 0590US7624366B2Clock aware placementIBM·Filed 2006·Granted Nov 24, 2009·27 cites·34 claims
- 0689US8495552B1Structured latch and local-clock-buffer planningCHO MINSIK·Filed 2012·Granted Jul 23, 2013·13 cites·15 claims
- 0786US8261226B1Network flow based module bottom surface metal pin assignmentBECKER WIREN DALE·Filed 2011·Granted Sep 4, 2012·13 cites·25 claims
- 0885US12412082B2Fine-grained per-vector scaling for neural network quantizationNVIDIA CORP·Filed 2020·Granted Sep 9, 2025·2 cites·21 claims
- 0985US12045307B2Fine-grained per-vector scaling for neural network quantizationNVIDIA CORP·Filed 2020·Granted Jul 23, 2024·2 cites·22 claims
- 1084US11972188B2Rail power density aware standard cell placement for integrated circuitsNVIDIA CORP·Filed 2021·Granted Apr 30, 2024·2 cites·28 claims
- 1183US11651194B2Layout parasitics and device parameter prediction using graph neural networksNVIDIA CORP·Filed 2020·Granted May 16, 2023·2 cites·17 claims
- 1282US8516412B2Soft hierarchy-based physical synthesis for large-scale, high-performance circuitsCHO MINSIK·Filed 2011·Granted Aug 20, 2013·8 cites·23 claims
- 1382US7467369B2Constrained detailed placementIBM·Filed 2006·Granted Dec 16, 2008·13 cites·8 claims
- 1481US7533360B1Flow based package pin assignmentIBM·Filed 2008·Granted May 12, 2009·11 cites·1 claims
- 1580US10545739B2LLVM-based system C compiler for architecture synthesisIBM·Filed 2016·Granted Jan 28, 2020·3 cites·19 claims
- 1680US10223491B2Integrated circuit design changes using through-silicon viasIBM·Filed 2017·Granted Mar 5, 2019·2 cites·15 claims
- 1779US9665674B2Automating a microarchitecture design exploration environmentIBM·Filed 2016·Granted May 30, 2017·2 cites·15 claims
- 1879US9569580B2Integrated circuit design changes using through-silicon viasIBM·Filed 2015·Granted Feb 14, 2017·2 cites·4 claims
- 1978US7464356B2Method and apparatus for diffusion based cell placement migrationIBM·Filed 2005·Granted Dec 9, 2008·7 cites·7 claims
- 2077US10956644B2Integrated circuit design changes using through-silicon viasIBM·Filed 2019·Granted Mar 23, 2021·1 cites·20 claims
- 2177US7882475B2Method to reduce the wirelength of analytical placement techniques by modulation of spreading forces vectorsIBM·Filed 2008·Granted Feb 1, 2011·8 cites·3 claims
- 2275US11645533B2IR drop prediction with maximum convolutional neural networkNVIDIA CORP·Filed 2020·Granted May 9, 2023·1 cites·21 claims
- 2375US8365114B2Logic modification synthesisIBM·Filed 2010·Granted Jan 29, 2013·5 cites·6 claims
- 2475US7076755B2Method for successive placement based refinement of a generalized cost functionIBM·Filed 2004·Granted Jul 11, 2006·24 cites·15 claims
- 2575US2025356106A1Lithography simulation using a neural networkNVIDIA CORP·Filed 2025·Application pending·0 cites
- 2672US12217151B2Layout parasitics and device parameter prediction using graph neural networksNVIDIA CORP·Filed 2023·Granted Feb 4, 2025·0 cites·18 claims
- 2770US8566761B2Network flow based datapath bit slicingXIANG HUA·Filed 2011·Granted Oct 22, 2013·3 cites·18 claims
- 2865US8112732B2System and computer program product for diffusion based cell placement migrationALPERT CHARLES J·Filed 2008·Granted Feb 7, 2012·3 cites·13 claims
- 2964US12277376B2Rail power density aware standard cell placement for integrated circuitsNVIDIA CORP·Filed 2024·Granted Apr 15, 2025·0 cites·23 claims
- 3063US12417334B2Lithography simulation using a neural networkNVIDIA CORP·Filed 2022·Granted Sep 16, 2025·0 cites·20 claims
- 3163US9412682B2Through-silicon via access device for integrated circuitsIBM·Filed 2014·Granted Aug 9, 2016·1 cites·11 claims
- 3262US12430485B2VLSI placement optimization using self-supervised graph clusteringNVIDIA CORP·Filed 2022·Granted Sep 30, 2025·0 cites·23 claims
- 3362US12169677B2Standard cell layout generation with applied artificial intelligenceNVIDIA CORP·Filed 2021·Granted Dec 17, 2024·0 cites·18 claims
- 3461US8756541B2Relative ordering circuit synthesisCHO MINSIK·Filed 2012·Granted Jun 17, 2014·1 cites·23 claims
- 3561US8656332B2Automated critical area allocation in a physical synthesized hierarchical designFLEISCHER BRUCE M·Filed 2009·Granted Feb 18, 2014·2 cites·20 claims
- 3661US8122400B2Logic difference synthesisHOPKINS JEREMY T·Filed 2009·Granted Feb 21, 2012·3 cites·19 claims
- 3761US2025181814A1Differentiable global routerNVIDIA CORP·Filed 2024·Application pending·0 cites
- 3858US12019967B2Routing connections in integrated circuits based on reinforcement learningNVIDIA CORP·Filed 2021·Granted Jun 25, 2024·0 cites·41 claims
- 3958US2024168390A1Machine learning for mask optimization in inverse lithography technologiesNVIDIA CORP·Filed 2023·Application pending·0 cites
- 4057US2025315590A1Large language model for standard cell layout design optimizationNVIDIA CORP·Filed 2025·Application pending·0 cites
- 4154US12373622B2Reducing crosstalk pessimism using GPU-accelerated gate simulation and machine learningNVIDIA CORP·Filed 2021·Granted Jul 29, 2025·0 cites·19 claims
- 4254US2025111112A1Transformer model-based clustering techniques for standard cell design automationNVIDIA CORP·Filed 2024·Application pending·0 cites
- 4353US9507891B1Automating a microarchitecture design exploration environmentIBM·Filed 2015·Granted Nov 29, 2016·0 cites·20 claims
- 4453US7882454B2Apparatus and method for improved test controllability and observability of random resistant logicIBM·Filed 2008·Granted Feb 1, 2011·2 cites·20 claims
- 4553US2022292335A1Reinforcement driven standard cell placementNVIDIA CORP·Filed 2022·Application pending·0 cites
- 4653US2024013033A1Large scale mask optimization with convolutional fourier neural operator and litho-guided self learningNVIDIA CORP·Filed 2023·Application pending·0 cites
- 4752US2025181806A1Learning-based placement for congestion mitigationNVIDIA CORP·Filed 2024·Application pending·0 cites
- 4850US12450467B2Determining IR dropNVIDIA CORP·Filed 2021·Granted Oct 21, 2025·0 cites·26 claims
- 4950US9563736B2Placement aware functional engineering change order extractionIBM·Filed 2014·Granted Feb 7, 2017·0 cites·10 claims
- 5050US2024411977A1Dynamic standard cell external pin methodology for routability-driven standard cell design automationNVIDIA CORP·Filed 2023·Application pending·0 cites
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →