Inventor · disambiguated record
Harold F. Webster
Also filed as: WEBSTER HAROLD F
22 granted patents·735 citations·filing 1975–1993
96Inventor score
Files withGEN ELECTRIC22
Top patents by PatentIndex Score
22 records- 0195US4361717AFluid cooled solar powered photovoltaic cellGEN ELECTRIC·Filed 1980·Granted Nov 30, 1982·117 cites·6 claims
- 0294US4831497AReduction of cross talk in interconnecting conductorsGEN ELECTRIC·Filed 1986·Granted May 16, 1989·95 cites·8 claims
- 0393US4392153ACooled semiconductor power module including structured strain buffers without dry interfacesGEN ELECTRIC·Filed 1978·Granted Jul 5, 1983·87 cites·23 claims
- 0491US4803450AMultilayer circuit board fabricated from siliconGEN ELECTRIC·Filed 1987·Granted Feb 7, 1989·73 cites·19 claims
- 0588US4996116AEnhanced direct bond structureGEN ELECTRIC·Filed 1989·Granted Feb 26, 1991·50 cites·49 claims
- 0685US4541035ALow loss, multilevel silicon circuit boardGEN ELECTRIC·Filed 1984·Granted Sep 10, 1985·57 cites·8 claims
- 0785US4366713AUltrasonic bond testing of semiconductor devicesGEN ELECTRIC·Filed 1981·Granted Jan 4, 1983·46 cites·10 claims
- 0883US4444352AMethod of thermo-compression diffusion bonding together metal surfacesGEN ELECTRIC·Filed 1981·Granted Apr 24, 1984·31 cites·29 claims
- 0971US4098452ALead bonding methodGEN ELECTRIC·Filed 1976·Granted Jul 4, 1978·27 cites·39 claims
- 1064US3990833ASwitching devices for photoflash unitGEN ELECTRIC·Filed 1975·Granted Nov 9, 1976·23 cites·22 claims
- 1159US5273203ACeramic-to-conducting-lead hermetic sealGEN ELECTRIC·Filed 1993·Granted Dec 28, 1993·26 cites·5 claims
- 1259US4413766AMethod of forming a conductor pattern including fine conductor runs on a ceramic substrateGEN ELECTRIC·Filed 1981·Granted Nov 8, 1983·20 cites·17 claims
- 1357US4118758APhotoflash lamp array having high voltage shorting type flash lamps and radiation sensitive switching elementsGEN ELECTRIC·Filed 1977·Granted Oct 3, 1978·4 cites·9 claims
- 1453US5241216ACeramic-to-conducting-lead hermetic sealGEN ELECTRIC·Filed 1989·Granted Aug 31, 1993·17 cites·20 claims
- 1549US4574299AThyristor packaging systemGEN ELECTRIC·Filed 1983·Granted Mar 4, 1986·13 cites·19 claims
- 1646US4745455ASilicon packages for power semiconductor devicesGEN ELECTRIC·Filed 1986·Granted May 17, 1988·16 cites·45 claims
- 1746US4287572AMethod for writing on archival target and target produced therebyGEN ELECTRIC·Filed 1979·Granted Sep 1, 1981·4 cites·17 claims
- 1841US4370590AMethod for writing on archival target and target produced therebyGEN ELECTRIC·Filed 1980·Granted Jan 25, 1983·4 cites·12 claims
- 1940US4796156ASelf packaging chip mountGEN ELECTRIC·Filed 1987·Granted Jan 3, 1989·9 cites·14 claims
- 2040US4672335APrinted circuit wiring board having a doped semi-conductive region terminationGEN ELECTRIC·Filed 1985·Granted Jun 9, 1987·5 cites·10 claims
- 2139US4908736ASelf packaging chip mountGEN ELECTRIC·Filed 1988·Granted Mar 13, 1990·8 cites·2 claims
- 2232US4914812AMethod of self-packaging an IC chipGEN ELECTRIC·Filed 1989·Granted Apr 10, 1990·3 cites·4 claims
Join the waitlist — get patent alerts
Get an alert when Harold F. Webster files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →