Inventor · disambiguated record
Hemanshu Bhatt
Also filed as: BHATT HEMANSHU · BHATT HEMANSHU D · BHATT HEMANSHU DEVSHANKAR
38 granted patents·6 pending applications·335 citations·filing 1996–2025
97Inventor score
Top patents by PatentIndex Score
44 records- 0189US5790366AHigh temperature electrode-barriers for ferroelectric and other capacitor structuresSHARP KK·Filed 1996·Granted Aug 4, 1998·77 cites·14 claims
- 0288US11569668B2System and method for dynamic balancing power in a battery packIGRENENERGI INC·Filed 2020·Granted Jan 31, 2023·6 cites·17 claims
- 0386US5807774ASimple method of fabricating ferroelectric capacitorsSHARP KK·Filed 1996·Granted Sep 15, 1998·70 cites·14 claims
- 0481US8552587B2Power conversion for distributed DC source arrayTYAGI SUNIT·Filed 2010·Granted Oct 8, 2013·8 cites·27 claims
- 0581US7955919B2Spacer-less transistor integration scheme for high-K gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe and strained silicon schemesLSI CORP·Filed 2007·Granted Jun 7, 2011·8 cites·21 claims
- 0681US6537923B1Process for forming integrated circuit structure with low dielectric constant material between closely spaced apart metal linesLSI LOGIC CORP·Filed 2000·Granted Mar 25, 2003·26 cites·17 claims
- 0777US7402770B2Nano structure electrode designLSI LOGIC CORP·Filed 2005·Granted Jul 22, 2008·10 cites·20 claims
- 0876US7205673B1Reduce or eliminate IMC cracking in post wire bonded dies by doping aluminum used in bond pads during Cu/Low-k BEOL processingLSI LOGIC CORP·Filed 2005·Granted Apr 17, 2007·7 cites·3 claims
- 0975US6982206B1Mechanism for improving the structural integrity of low-k filmsLSI LOGIC CORP·Filed 2003·Granted Jan 3, 2006·20 cites·19 claims
- 1074US6649537B1Intermittent pulsed oxidation processLSI LOGIC CORP·Filed 2001·Granted Nov 18, 2003·16 cites·18 claims
- 1173US12040635B2System and method for dynamically balancing power from distributed power sources in a battery packIGRENENERGI INC·Filed 2021·Granted Jul 16, 2024·1 cites·23 claims
- 1273US6967177B1Temperature control systemLSI LOGIC CORP·Filed 2000·Granted Nov 22, 2005·14 cites·7 claims
- 1372US8552560B2Alternate pad structures/passivation inegration schemes to reduce or eliminate IMC cracking in post wire bonded dies during Cu/Low-K BEOL processingBHATT HEMANSHU·Filed 2005·Granted Oct 8, 2013·7 cites·3 claims
- 1470US7531442B2Eliminate IMC cracking in post wirebonded dies: macro level stress reduction by modifying dielectric/metal film stack in be layers during Cu/Low-K processingLSI CORP·Filed 2005·Granted May 12, 2009·5 cites·4 claims
- 1567US7384801B2Integrated circuit with inductor having horizontal magnetic flux linesLSI CORP·Filed 2007·Granted Jun 10, 2008·3 cites·8 claims
- 1666US7456076B2Techniques for forming passive devices during semiconductor back-end processingLSI CORP·Filed 2006·Granted Nov 25, 2008·2 cites·10 claims
- 1765US8304314B2Method of forming an MOS transistorPEARSE JEFFREY·Filed 2008·Granted Nov 6, 2012·4 cites·15 claims
- 1864US7361965B2Method and apparatus for redirecting void diffusion away from vias in an integrated circuit designLSI LOGIC CORP·Filed 2005·Granted Apr 22, 2008·2 cites·18 claims
- 1962US7436040B2Method and apparatus for diverting void diffusion in integrated circuit conductorsLSI CORP·Filed 2005·Granted Oct 14, 2008·2 cites·13 claims
- 2060US9577548B2Power conversion for distributed DC source arrayIGRENENERGI INC·Filed 2013·Granted Feb 21, 2017·1 cites·26 claims
- 2160US8772865B2MOS transistor structureSEMICONDUCTOR COMPONENTS IND·Filed 2012·Granted Jul 8, 2014·1 cites·8 claims
- 2260US6583026B1Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structureLSI LOGIC CORP·Filed 2001·Granted Jun 24, 2003·7 cites·23 claims
- 2360US6495419B1Nonvolatile memory in CMOS process flowLSI LOGIC CORP·Filed 2000·Granted Dec 17, 2002·8 cites·18 claims
- 2458US6338992B1Programmable read only memory in CMOS process flowLSI LOGIC CORP·Filed 2000·Granted Jan 15, 2002·7 cites·18 claims
- 2557US11183839B2DC-DC power conversion systemIGRENENERGI INC·Filed 2017·Granted Nov 23, 2021·1 cites·9 claims
- 2656US9739934B2Method for producing fibers having optical effect-producing nanostructuresEMPIRE TECHNOLOGY DEV LLC·Filed 2015·Granted Aug 22, 2017·0 cites·17 claims
- 2756US7253497B2Integrated circuit with inductor having horizontal magnetic flux linesLSI CORP·Filed 2003·Granted Aug 7, 2007·6 cites·5 claims
- 2856US2025236971A1Electrolyser system and designBHATT HEMANSHU DEVSHANKAR·Filed 2025·Application pending·0 cites
- 2955US6495881B1Programmable read only memory in CMOS process flowLSI LOGIC CORP·Filed 2001·Granted Dec 17, 2002·6 cites·2 claims
- 3053US7582566B2Method for redirecting void diffusion away from vias in an integrated circuit designLSI LOGIC CORP·Filed 2008·Granted Sep 1, 2009·0 cites·11 claims
- 3151US6574525B1In situ measurementLSI LOGIC CORP·Filed 2002·Granted Jun 3, 2003·3 cites·20 claims
- 3250US7259083B2Local interconnect manufacturing processLSI CORP·Filed 2004·Granted Aug 21, 2007·5 cites·10 claims
- 3350US2014030541A1Alternate pad structures/passivation integration schemes to reduce or eliminate imc cracking in post wire bonded dies during cu/low-k beol processingLSI CORP·Filed 2013·Application pending·0 cites
- 3448US2023179002A1System and method for dynamic balancing power in a battery packIGRENENERGI INC·Filed 2023·Application pending·0 cites
- 3548US2005279284A1Temperature control systemLSI LOGIC CORP·Filed 2005·Application pending·0 cites
- 3647US6521520B1Semiconductor wafer arrangement and method of processing a semiconductor waferLSI LOGIC CORP·Filed 2001·Granted Feb 18, 2003·1 cites·12 claims
- 3744US8940199B2Method for producing fibers having optical effect-producing nanostructuresBHATT HEMANSHU D·Filed 2011·Granted Jan 27, 2015·0 cites·9 claims
- 3842US7122436B2Techniques for forming passive devices during semiconductor back-end processingLSI LOGIC CORP·Filed 2004·Granted Oct 17, 2006·0 cites·10 claims
- 3941US7915122B2Self-aligned cell integration schemeNANTERO INC·Filed 2005·Granted Mar 29, 2011·1 cites·2 claims
- 4041US6707114B1Semiconductor wafer arrangement of a semiconductor waferLSI LOGIC CORP·Filed 2002·Granted Mar 16, 2004·0 cites·8 claims
- 4140US8076779B2Reduction of macro level stresses in copper/low-K wafersSUN SEY-SHING·Filed 2005·Granted Dec 13, 2011·0 cites·4 claims
- 4238US2005191812A1Spacer-less transistor integration scheme for high-k gate dielectrics and small gate-to-gate spaces applicable to Si, SiGe strained silicon schemesLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 4338US2006063338A1Shallow trench isolation depth extension using oxygen implantationLSI LOGIC CORP·Filed 2004·Application pending·0 cites
- 4435US6482075B1Process for planarizing an isolation structure in a substrateLSI LOGIC CORP·Filed 2000·Granted Nov 19, 2002·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →