Inventor · disambiguated record
Hemlata Gupta
Also filed as: GUPTA HEMLATA
15 granted patents·6 pending applications·20 citations·filing 2009–2023
88Inventor score
Top patents by PatentIndex Score
21 records- 0182US9985843B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2015·Granted May 29, 2018·3 cites·20 claims
- 0277US10902167B1Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuitsIBM·Filed 2019·Granted Jan 26, 2021·2 cites·20 claims
- 0377US9495218B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2016·Granted Nov 15, 2016·2 cites·1 claims
- 0475US9910954B2Programmable clock division methodology with in-context frequency checkingIBM·Filed 2016·Granted Mar 6, 2018·2 cites·17 claims
- 0571US8549452B2Method for supporting multiple libraries characterized at different process, voltage and temperature pointsBANERJI REVANTA·Filed 2010·Granted Oct 1, 2013·5 cites·20 claims
- 0668US9940431B2Accurate statistical timing for boundary gates of hierarchical timing modelsIBM·Filed 2016·Granted Apr 10, 2018·1 cites·12 claims
- 0767US9977850B2Callback based constraint processing for clock domain independenceIBM·Filed 2016·Granted May 22, 2018·1 cites·19 claims
- 0862US8056038B2Method for efficiently checkpointing and restarting static timing analysis of an integrated circuit chipIBM·Filed 2009·Granted Nov 8, 2011·2 cites·16 claims
- 0957US8776004B2Method for improving static timing analysis and optimizing circuits using reverse mergeBORKAM FRANK·Filed 2011·Granted Jul 8, 2014·2 cites·15 claims
- 1056US10354046B2Programmable clock division methodology with in-context frequency checkingIBM·Filed 2017·Granted Jul 16, 2019·0 cites·11 claims
- 1156US10169527B2Accurate statistical timing for boundary gates of hierarchical timing modelsIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 1256US10169503B2Callback based constraint processing for clock domain independenceIBM·Filed 2018·Granted Jan 1, 2019·0 cites·19 claims
- 1355US9853866B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2017·Granted Dec 26, 2017·0 cites·1 claims
- 1455US9608868B2Efficient parallel processing of a network with conflict constraints between nodesIBM·Filed 2016·Granted Mar 28, 2017·0 cites·1 claims
- 1553US2024386175A1Timing analysis for non-scan latchesIBM·Filed 2023·Application pending·0 cites
- 1653US2025005244A1Timing constraint auto-creation for integrated circuit testingIBM·Filed 2023·Application pending·0 cites
- 1751US2024330556A1Location aware timing analysis of a digital integrated circuitIBM·Filed 2023·Application pending·0 cites
- 1851US2024330551A1Timing analysis of a digital integrated circuit using intent based timing constraintsIBM·Filed 2023·Application pending·0 cites
- 1941US9659121B1Deterministic and statistical timing modeling for differential circuitsIBM·Filed 2015·Granted May 23, 2017·0 cites·20 claims
- 2041US2015073738A1Determining process variation using device threshold sensitivitesIBM·Filed 2013·Application pending·0 cites
- 2141US2019362043A1Dynamic update of macro timing models during higher-level timing analysisIBM·Filed 2018·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →