Inventor · disambiguated record
Heiko Kalte
Also filed as: KALTE HEIKO
23 granted patents·10 pending applications·15 citations·filing 2014–2025
90Inventor score
Files withDSPACE GMBH33
Top patents by PatentIndex Score
33 records- 0181US9870440B2Method for automatically generating a netlist of an FPGA programDSPACE GMBH·Filed 2015·Granted Jan 16, 2018·4 cites·21 claims
- 0279US10311193B2Alteration of a signal value for an FPGA at runtimeDSPACE GMBH·Filed 2015·Granted Jun 4, 2019·4 cites·17 claims
- 0378US9235425B2Random access to signal values of an FPGA at runtimeDSPACE GMBH·Filed 2014·Granted Jan 12, 2016·4 cites·10 claims
- 0468US10394989B2Method for creating an FPGA netlistDSPACE GMBH·Filed 2017·Granted Aug 27, 2019·1 cites·15 claims
- 0568US10083043B2Random access to signal values of an FPGA at runtimeDSPACE GMBH·Filed 2015·Granted Sep 25, 2018·1 cites·6 claims
- 0664US12348236B2Method for changing a bitwidth of an FPGA configurationDSPACE GMBH·Filed 2022·Granted Jul 1, 2025·0 cites·12 claims
- 0760US10318687B2Implementing a constant in FPGA codeDSPACE GMBH·Filed 2015·Granted Jun 11, 2019·1 cites·14 claims
- 0857US2025021462A1Method for fpga build and initializationDSPACE GMBH·Filed 2024·Application pending·0 cites
- 0956US2025260405A1Programmable gate array and method of generating configuration data for programming a gate arrayDSPACE GMBH·Filed 2025·Application pending·0 cites
- 1055US12197336B2Method for effectively increasing a memory on an FPGADSPACE GMBH·Filed 2023·Granted Jan 14, 2025·0 cites·15 claims
- 1153US12253876B2Method for programming an FPGADSPACE GMBH·Filed 2023·Granted Mar 18, 2025·0 cites·12 claims
- 1253US12079601B2Computer-implemented method for creating a hierarchical block diagramDSPACE GMBH·Filed 2022·Granted Sep 3, 2024·0 cites·14 claims
- 1353US11187748B2Procedure for reviewing an FPGA-programDSPACE GMBH·Filed 2019·Granted Nov 30, 2021·0 cites·14 claims
- 1453US10706196B2Incremental generation of an FPGA implementation with a graph-based similarity searchDSPACE GMBH·Filed 2018·Granted Jul 7, 2020·0 cites·16 claims
- 1553US2024028457A1Method and device for detecting errors in routes and calculations within an fpgaDSPACE GMBH·Filed 2023·Application pending·0 cites
- 1652US12341512B2Method for programming an FPGADSPACE GMBH·Filed 2022·Granted Jun 24, 2025·0 cites·10 claims
- 1750US11586793B2Method for producing an association listDSPACE GMBH·Filed 2018·Granted Feb 21, 2023·0 cites·11 claims
- 1850US11222159B2Method, computer-based system and computer program product for planning partitions for a programmable gate arrayDSPACE GMBH·Filed 2021·Granted Jan 11, 2022·0 cites·13 claims
- 1950US2023333892A1Method for documenting computing steps of a real time system executed on a computer core of a processor, processor and real time systemDSPACE GMBH·Filed 2023·Application pending·0 cites
- 2047US2023082540A1Method of adding another circuit componentDSPACE GMBH·Filed 2022·Application pending·0 cites
- 2146US12158849B2Method for data communication between subregions of an FPGADSPACE GMBH·Filed 2022·Granted Dec 3, 2024·0 cites·14 claims
- 2246US2024267429A1Method and system for transforming recorded communication dataDSPACE GMBH·Filed 2024·Application pending·0 cites
- 2345US11843514B2Computer-implemented method for restructuring a predefined distributed real-time simulation networkDSPACE GMBH·Filed 2021·Granted Dec 12, 2023·0 cites·18 claims
- 2444US10224930B2Method for detecting the topology of electrical wiringDSPACE GMBH·Filed 2018·Granted Mar 5, 2019·0 cites·14 claims
- 2543US2019138310A1Method for reading out variables from an fpgaDSPACE GMBH·Filed 2018·Application pending·0 cites
- 2642US11017141B2Method for troubleshooting the program logic of a system of distributed progammable gate arraysDSPACE GMBH·Filed 2020·Granted May 25, 2021·0 cites·12 claims
- 2742US10223077B2Determination of signals for readback from FPGADSPACE GMBH·Filed 2015·Granted Mar 5, 2019·0 cites·15 claims
- 2840US11442884B2Method for programming a programmable gate array in a distributed computer systemDSPACE GMBH·Filed 2021·Granted Sep 13, 2022·0 cites·17 claims
- 2939US9628085B1Method and device for accelerated access to signals of a programmable logic deviceDSPACE GMBH·Filed 2016·Granted Apr 18, 2017·0 cites·10 claims
- 3039US2017329732A1Method for temporally synchronizing the output and/or temporally synchronizing the processing of signalsDSPACE GMBH·Filed 2017·Application pending·0 cites
- 3138US10102325B2Method for determining the power consumption of a programmable logic deviceDSPACE GMBH·Filed 2016·Granted Oct 16, 2018·0 cites·18 claims
- 3238US2020145486A1Computer network with a first and a second synchronizing signal transmitterDSPACE GMBH·Filed 2019·Application pending·0 cites
- 3336US2019165996A1Method for operating a real -time-capable simulation network having multiple network nodes for computing a simulation model, also computer program product relating thereto, and computer-readable storage mediumDSPACE GMBH·Filed 2017·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →