Inventor · disambiguated record
Hideya Akashi
Also filed as: AKASHI HIDEYA
15 granted patents·3 pending applications·574 citations·filing 1995–2003
95Inventor score
Technology areasG06F
Files withHITACHI LTD15
Top patents by PatentIndex Score
18 records- 0196US6789173B1Node controller for performing cache coherence control and memory-shared multiprocessor systemHITACHI LTD·Filed 2000·Granted Sep 7, 2004·157 cites·20 claims
- 0284US6546471B1Shared memory multiprocessor performing cache coherencyHITACHI LTD·Filed 2000·Granted Apr 8, 2003·34 cites·4 claims
- 0381US6874053B2Shared memory multiprocessor performing cache coherence control and node controller thereforHITACHI LTD·Filed 2003·Granted Mar 29, 2005·27 cites·5 claims
- 0479US6993633B1Computer system utilizing speculative read requests to cache memoryHITACHI LTD·Filed 2000·Granted Jan 31, 2006·30 cites·24 claims
- 0579US6606688B1Cache control method and cache controllerHITACHI LTD·Filed 2000·Granted Aug 12, 2003·31 cites·17 claims
- 0678US6516391B1Multiprocessor system and methods for transmitting memory access transactions for the sameHITACHI LTD·Filed 2000·Granted Feb 4, 2003·28 cites·10 claims
- 0777US6088770AShared memory multiprocessor performing cache coherencyHITACHI LTD·Filed 1998·Granted Jul 11, 2000·67 cites·11 claims
- 0873US5778429AParallel processor system including a cache memory subsystem that has independently addressable local and remote data areasHITACHI LTD·Filed 1995·Granted Jul 7, 1998·64 cites·40 claims
- 0969US6591325B1Method and apparatus of out-of-order transaction processing using request side queue pointer and response side queue pointerHITACHI LTD·Filed 2000·Granted Jul 8, 2003·14 cites·8 claims
- 1068US6636926B2Shared memory multiprocessor performing cache coherence control and node controller thereforHITACHI LTD·Filed 2000·Granted Oct 21, 2003·12 cites·19 claims
- 1168US6438653B1Cache memory control circuit including summarized cache tag memory summarizing cache tag information in parallel processor systemHITACHI LTD·Filed 1999·Granted Aug 20, 2002·53 cites·8 claims
- 1263US6839806B2Cache system with a cache tag memory and a cache tag bufferHITACHI LTD·Filed 2001·Granted Jan 4, 2005·9 cites·23 claims
- 1357US6119150AMessage passing distributed shared memory system that eliminates unnecessary software controlled cache flushes or purgesHITACHI LTD·Filed 1997·Granted Sep 12, 2000·33 cites·6 claims
- 1455US7206818B2Shared memory multiprocessor systemHITACHI LTD·Filed 2003·Granted Apr 17, 2007·4 cites·10 claims
- 1542US2002198924A1Process scheduling method based on active program characteristics on process execution, programs using this method and data processorsFiled 2002·Application pending·0 cites
- 1641US2002040414A1Multiprocessor system and transaction control method for the sameFiled 2001·Application pending·0 cites
- 1740US6295579B1Parallel processor system including a cache memory subsystem that has independently addressable local and remote data areasHITACHI LTD·Filed 1998·Granted Sep 25, 2001·11 cites·4 claims
- 1840US2001013080A1Multiprocessor system and transaction control method for the sameFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →