Inventor · disambiguated record
Hidetaka Horiuchi
Also filed as: HORIUCHI HIDETAKA
6 granted patents·1 pending application·122 citations·filing 1999–2011
85Inventor score
Top patents by PatentIndex Score
7 records- 0192US7615445B2Methods of reducing coupling between floating gates in nonvolatile memorySANDISK CORP·Filed 2006·Granted Nov 10, 2009·19 cites·11 claims
- 0289US6558505B2Method and apparatus for processing semiconductor substratesKAWASAKI MICROELECTRONICS INC·Filed 2002·Granted May 6, 2003·41 cites·18 claims
- 0377US6547921B2Method and apparatus for processing semiconductor substratesKAWASAKI MICROELECTRONICS INC·Filed 2002·Granted Apr 15, 2003·17 cites·41 claims
- 0476US6447853B1Method and apparatus for processing semiconductor substratesKAWASAKI MICROELECTRONICS INC·Filed 1999·Granted Sep 10, 2002·39 cites·20 claims
- 0574US7910434B2Method of reducing coupling between floating gates in nonvolatile memorySANDISK CORP·Filed 2009·Granted Mar 22, 2011·4 cites·8 claims
- 0668US8288225B2Method of reducing coupling between floating gates in nonvolatile memoryCHIEN HENRY·Filed 2011·Granted Oct 16, 2012·2 cites·18 claims
- 0739US2008074920A1Nonvolatile Memory with Reduced Coupling Between Floating GatesCHIEN HENRY·Filed 2006·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →