Inventor · disambiguated record
Hirohide Sugahara
Also filed as: SUGAHARA HIROHIDE
25 granted patents·1 pending application·595 citations·filing 1991–2004
97Inventor score
Top patents by PatentIndex Score
26 records- 0188US6732212B2Launch raw packet on remote interruptFUJITSU LTD·Filed 2001·Granted May 4, 2004·50 cites·22 claims
- 0286US5890217ACoherence apparatus for cache of multiprocessorFUJITSU LTD·Filed 1996·Granted Mar 30, 1999·150 cites·60 claims
- 0385US6901451B1PCI bridge over networkFUJITSU LTD·Filed 2000·Granted May 31, 2005·42 cites·26 claims
- 0485US6684281B1Fast delivery of interrupt message over networkFUJITSU LTD·Filed 2000·Granted Jan 27, 2004·41 cites·17 claims
- 0575US7424628B2Serial type interface circuit, power saving method thereof, and device having serial interfaceFUJITSU LTD·Filed 2004·Granted Sep 9, 2008·24 cites·17 claims
- 0674US6799219B1Method and apparatus for avoiding starvation in computer networkFUJITSU LTD·Filed 2000·Granted Sep 28, 2004·19 cites·15 claims
- 0772US6804673B2Access assurance for remote memory access over networkFUJITSU LTD·Filed 2001·Granted Oct 12, 2004·17 cites·13 claims
- 0865US7818479B2Interface apparatus and packet transfer methodTOSHIBA STORAGE DEVICE CORP·Filed 2004·Granted Oct 19, 2010·15 cites·12 claims
- 0964US6092173AMultiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer systemFUJITSU LTD·Filed 1997·Granted Jul 18, 2000·43 cites·8 claims
- 1060US7103128B2Data synchronization circuit and communication interface circuitFUJITSU LTD·Filed 2002·Granted Sep 5, 2006·6 cites·4 claims
- 1157US6877039B2Simplified pipeline writes over a networkFUJITSU LTD·Filed 2001·Granted Apr 5, 2005·4 cites·11 claims
- 1257US5634037AMultiprocessor system having a shared memory with exclusive access for a requesting processor which is maintained until normal completion of a process and for retrying the process when not normally completedFUJITSU LTD·Filed 1994·Granted May 27, 1997·31 cites·10 claims
- 1354US7664042B2Storage control apparatus, storage apparatus, storage control method, and computer-readable recording medium for executing a command based on data in received packetTOSHIBA STORAGE DEVICE CORP·Filed 2004·Granted Feb 16, 2010·6 cites·20 claims
- 1451US6038674AMultiprocessor, memory accessing method for multiprocessor, transmitter and receiver in data transfer system, data transfer system, and bus control method for data transfer systemFUJITSU LTD·Filed 1999·Granted Mar 14, 2000·23 cites·4 claims
- 1549US5428768ASystem for checking comparison check function of information processing apparatusFUJITSU LTD·Filed 1993·Granted Jun 27, 1995·21 cites·5 claims
- 1648US5761728AAsynchronous access system controlling processing modules making requests to a shared system memoryFUJITSU LTD·Filed 1996·Granted Jun 2, 1998·22 cites·8 claims
- 1748US5500945AApparatus and method for controlling a system bus of a multiprocessor systemFUJITSU LTD·Filed 1995·Granted Mar 19, 1996·21 cites·6 claims
- 1845US5727151AMessage control system specifying message storage buffer for data communication system with general purpose and arbitrary form buffersFUJITSU LTD·Filed 1991·Granted Mar 10, 1998·17 cites·21 claims
- 1942US6678758B2Dynamic queuing for read/write requestsFUJITSU LTD·Filed 2001·Granted Jan 13, 2004·0 cites·15 claims
- 2042US2003131166A1Information processing system and interface apparatusFUJITSU LTD·Filed 2002·Application pending·0 cites
- 2139US5737573AAsynchronous access system having an internal buffer control circuit which invalidates an internal bufferFUJITSU LTD·Filed 1996·Granted Apr 7, 1998·12 cites·8 claims
- 2234US5708795AAsynchronous access system for multiprocessor system and processor module used in the asynchronous access systemFUJITSU LTD·Filed 1994·Granted Jan 13, 1998·7 cites·15 claims
- 2333US5734845ABus arbiter provided in a multi-processor systemFUJITSU LTD·Filed 1994·Granted Mar 31, 1998·6 cites·16 claims
- 2433US5592624AData communication for controlling message transmission and reception among processing modules using information stored in descriptor to form a loosely coupled multiprocessing systemFUJITSU LTD·Filed 1991·Granted Jan 7, 1997·6 cites·15 claims
- 2533US5402421ABus control device and bus control methodFUJITSU LTD·Filed 1993·Granted Mar 28, 1995·7 cites·5 claims
- 2631US5704056ACache-data transfer systemFUJITSU LTD·Filed 1996·Granted Dec 30, 1997·5 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →