Inventor · disambiguated record
Hirofumi Yonetoku
Also filed as: YONETOKU HIROFUMI
4 granted patents·38 citations·filing 1996–2015
72Inventor score
Technology areasG01R
Top patents by PatentIndex Score
4 records- 0163US9081058B2Scan test circuit, test pattern generation control circuit, and scan test control methodRENESAS ELECTRONICS CORP·Filed 2013·Granted Jul 14, 2015·1 cites·34 claims
- 0260US6836867B2Method of generating a pattern for testing a logic circuit and apparatus for doing the sameNEC ELECTRONICS CORP·Filed 2001·Granted Dec 28, 2004·12 cites·24 claims
- 0357US5719881ATest pattern generating apparatus and methodNEC CORP·Filed 1996·Granted Feb 17, 1998·25 cites·7 claims
- 0455US9341674B2Scan test circuit, test pattern generation control circuit, and scan test control methodRENESAS ELECTRONICS CORP·Filed 2015·Granted May 17, 2016·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →