Inventor · disambiguated record
Howard S. David
Also filed as: DAVID HOWARD · DAVID HOWARD S
36 granted patents·4 pending applications·731 citations·filing 1992–2023
98Inventor score
Top patents by PatentIndex Score
40 records- 0198US6795899B2Memory system with burst length shorter than prefetch lengthINTEL CORP·Filed 2002·Granted Sep 21, 2004·208 cites·35 claims
- 0289US7804733B2System and method for memory phase sheddingINTEL CORP·Filed 2007·Granted Sep 28, 2010·22 cites·13 claims
- 0388US7036053B2Two dimensional data eye centering for source synchronous data transfersINTEL CORP·Filed 2002·Granted Apr 25, 2006·63 cites·36 claims
- 0487US8122265B2Power management using adaptive thermal throttlingRADHAKRISHNAN SIVAKUMAR·Filed 2006·Granted Feb 21, 2012·20 cites·22 claims
- 0587US7318130B2System and method for thermal throttling of memory modulesINTEL CORP·Filed 2004·Granted Jan 8, 2008·59 cites·24 claims
- 0687US6832177B2Method of addressing individual memory devices on a memory moduleINTEL CORP·Filed 2002·Granted Dec 14, 2004·42 cites·32 claims
- 0784US7864604B2Multiple address outputs for programming the memory register set differently for different DRAM devicesINTEL CORP·Filed 2007·Granted Jan 4, 2011·15 cites·14 claims
- 0882US8327172B2Adaptive memory frequency scalingDAVID HOWARD S·Filed 2010·Granted Dec 4, 2012·7 cites·15 claims
- 0981US6925534B2Distributed memory module cache prefetchINTEL CORP·Filed 2001·Granted Aug 2, 2005·32 cites·21 claims
- 1081US6865646B2Segmented distributed memory module cacheINTEL CORP·Filed 2001·Granted Mar 8, 2005·32 cites·12 claims
- 1180US8412479B2Memory power estimation by means of calibrated weights and activity countersDAVID HOWARD S·Filed 2010·Granted Apr 2, 2013·6 cites·10 claims
- 1278US8438410B2Memory power management via dynamic memory operation statesDAVID HOWARD S·Filed 2010·Granted May 7, 2013·5 cites·26 claims
- 1375US7269025B2Ballout for bufferINTEL CORP·Filed 2004·Granted Sep 11, 2007·22 cites·23 claims
- 1474US7844876B2Temperature sampling in electronic devicesINTEL CORP·Filed 2006·Granted Nov 30, 2010·9 cites·24 claims
- 1573US8046559B2Memory rank burst schedulingINTEL CORP·Filed 2008·Granted Oct 25, 2011·6 cites·22 claims
- 1671US8738937B2Method and apparatus to limit memory powerDAVID HOWARD S·Filed 2010·Granted May 27, 2014·3 cites·18 claims
- 1770US7389387B2Distributed memory module cache writebackINTEL CORP·Filed 2001·Granted Jun 17, 2008·15 cites·13 claims
- 1867US6938129B2Distributed memory module cacheINTEL CORP·Filed 2001·Granted Aug 30, 2005·12 cites·15 claims
- 1966US12032018B2System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controllerHUAWEI TECH CO LTD·Filed 2023·Granted Jul 9, 2024·0 cites·17 claims
- 2065US11624780B2System and method for receiver equalization and stressed eye testing methodology for DDR5 memory controllerHUAWEI TECH CO LTD·Filed 2020·Granted Apr 11, 2023·0 cites·20 claims
- 2164US7188208B2Side-by-side inverted memory address and command busesINTEL CORP·Filed 2004·Granted Mar 6, 2007·9 cites·20 claims
- 2263US6931505B2Distributed memory module cache command formattingINTEL CORP·Filed 2001·Granted Aug 16, 2005·9 cites·28 claims
- 2361US6026460AMethod and apparatus for sequencing system bus grants and disabling a posting buffer in a bus bridge to improve bus efficiencyINTEL CORP·Filed 1996·Granted Feb 15, 2000·40 cites·8 claims
- 2460US5537640AAsynchronous modular bus architecture with cache consistencyINTEL CORP·Filed 1994·Granted Jul 16, 1996·35 cites·11 claims
- 2558US6880044B2Distributed memory module cache tag look-upINTEL CORP·Filed 2001·Granted Apr 12, 2005·6 cites·27 claims
- 2657US6976121B2Apparatus and method to track command signal occurrence for DRAM data transferINTEL CORP·Filed 2002·Granted Dec 13, 2005·5 cites·26 claims
- 2756US8661284B2Method and system to improve the operations of a registered memory moduleALEXANDER JAMES W·Filed 2013·Granted Feb 25, 2014·1 cites·6 claims
- 2855US7626884B2Optimizing mode register set commandsINTEL CORP·Filed 2007·Granted Dec 1, 2009·3 cites·14 claims
- 2949US8375241B2Method and system to improve the operations of a registered memory moduleINTEL CORP·Filed 2009·Granted Feb 12, 2013·1 cites·6 claims
- 3048US7958380B2Coarsely controlling memory power statesINTEL CORP·Filed 2007·Granted Jun 7, 2011·0 cites·15 claims
- 3148US7392339B2Partial bank DRAM prechargeINTEL CORP·Filed 2003·Granted Jun 24, 2008·5 cites·29 claims
- 3246US5668949ASystem utilizing multiple address decode resources and decoder receiving address determines address corresponding to resource based on select and ready signals by that particular resourceINTEL CORP·Filed 1995·Granted Sep 16, 1997·19 cites·14 claims
- 3346US2015178092A1Hierarchical and parallel partition networksMISHRA ASIT K·Filed 2013·Application pending·0 cites
- 3444US9448956B2Stuffing bits on a memory bus between data burstsKESLING WILLIAM DAWSON·Filed 2012·Granted Sep 20, 2016·0 cites·19 claims
- 3542US5437021AProgrammable dedicated timer operating on a clock independent of processor timerINTEL CORP·Filed 1992·Granted Jul 25, 1995·14 cites·27 claims
- 3641US2008040408A1Temperature sampling in electronic devicesWYATT DAVID·Filed 2006·Application pending·0 cites
- 3741US2003105932A1Emulation of memory clock enable pin and use of chip select for memory power controlFiled 2001·Application pending·0 cites
- 3833US6976120B2Apparatus and method to track flag transitions for DRAM data transferINTEL CORP·Filed 2002·Granted Dec 13, 2005·0 cites·18 claims
- 3933US2005108460A1Partial bank DRAM refreshINTEL CORP·Filed 2003·Application pending·0 cites
- 4032US5590289AMethod and apparatus for initializing a computer system having central and distributed address decode memory bus resourcesINTEL CORP·Filed 1995·Granted Dec 31, 1996·6 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →