Inventor · disambiguated record
Hong Lin
Also filed as: LIN HONG · LIN Hong-Che
16 granted patents·6 pending applications·306 citations·filing 2002–2025
94Inventor score
Top patents by PatentIndex Score
22 records- 0191US6864152B1Fabrication of trenches with multiple depths on the same substrateLSI LOGIC CORP·Filed 2003·Granted Mar 8, 2005·94 cites·10 claims
- 0290US7553772B1Process and apparatus for simultaneous light and radical surface treatment of integrated circuit structureLSI CORP·Filed 2005·Granted Jun 30, 2009·19 cites·14 claims
- 0387US9843602B2Login failure sequence for detecting phishingTREND MICRO INC·Filed 2016·Granted Dec 12, 2017·6 cites·11 claims
- 0486US7341978B2Superconductor wires for back end interconnectsLSI LOGIC CORP·Filed 2005·Granted Mar 11, 2008·17 cites·12 claims
- 0583US6743669B1Method of reducing leakage using Si3N4 or SiON block dielectric filmsLSI LOGIC CORP·Filed 2002·Granted Jun 1, 2004·33 cites·19 claims
- 0679US6746925B1High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidationLSI LOGIC CORP·Filed 2003·Granted Jun 8, 2004·27 cites·19 claims
- 0777US7365015B2Damascene replacement metal gate process with controlled gate profile and length using Si1-xGex as sacrificial materialLSI LOGIC CORP·Filed 2004·Granted Apr 29, 2008·20 cites·14 claims
- 0876US2024063270A1High electron mobility transistor epitaxial structureGLOBALWAFERS CO LTD·Filed 2023·Application pending·0 cites
- 0975US7405116B2Application of gate edge liner to maintain gate length CD in a replacement gate transistor flowLSI CORP·Filed 2004·Granted Jul 29, 2008·18 cites·9 claims
- 1072US6794304B1Method and apparatus for reducing microtrenching for borderless vias created in a dual damascene processLSI LOGIC CORP·Filed 2003·Granted Sep 21, 2004·22 cites·20 claims
- 1171US6806038B2Plasma passivationLSI LOGIC CORP·Filed 2002·Granted Oct 19, 2004·16 cites·16 claims
- 1270US10027708B2Login failure sequence for detecting phishingTREND MICRO INC·Filed 2017·Granted Jul 17, 2018·1 cites·11 claims
- 1370US6818516B1Selective high k dielectrics removalLSI LOGIC CORP·Filed 2003·Granted Nov 16, 2004·14 cites·20 claims
- 1468US7189628B1Fabrication of trenches with multiple depths on the same substrateLSI LOGIC CORP·Filed 2004·Granted Mar 13, 2007·15 cites·7 claims
- 1558US2024170564A1Epitaxial structureGLOBALWAFERS CO LTD·Filed 2023·Application pending·0 cites
- 1657US2025359239A1Method of manufacturing epitaxial structure and epitaxial structureGLOBALWAFERS CO LTD·Filed 2025·Application pending·0 cites
- 1757US2023378278A1Novel buffer layer structure to improve gan semiconductorsGLOBALWAFERS CO LTD·Filed 2023·Application pending·0 cites
- 1852US7081406B2Interconnect dielectric tuningLSI LOGIC CORP·Filed 2004·Granted Jul 25, 2006·4 cites·13 claims
- 1949US7259462B1Interconnect dielectric tuningLSI CORP·Filed 2006·Granted Aug 21, 2007·0 cites·4 claims
- 2047US2008150090A1DAMASCENE REPLACEMENT METAL GATE PROCESS WITH CONTROLLED GATE PROFILE AND LENGTH USING Si1-xGex AS SACRIFICIAL MATERIALLSI LOGIC CORP·Filed 2008·Application pending·0 cites
- 2146US8384165B2Application of gate edge liner to maintain gate length CD in a replacement gate transistor flowLSI CORP·Filed 2008·Granted Feb 26, 2013·0 cites·16 claims
- 2238US2005064716A1Plasma removal of high k metal oxideFiled 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →