Inventor · disambiguated record
Hoong Chin Ng
Also filed as: NG HOONG CHIN
9 granted patents·1 pending application·9 citations·filing 2015–2024
78Inventor score
Top patents by PatentIndex Score
10 records- 0183US9571075B1Input voltage clamp with signal splitting and cross-over capabilitiesALTERA CORP·Filed 2015·Granted Feb 14, 2017·6 cites·19 claims
- 0276US9647663B1Differential input buffer circuits and methodsALTERA CORP·Filed 2016·Granted May 9, 2017·3 cites·20 claims
- 0359US12469541B2Offset calibration method and apparatus for high bandwidth memory 3 (HBM3)SKYECHIP SDN BHD·Filed 2024·Granted Nov 11, 2025·0 cites·10 claims
- 0448US9793893B1Differential input buffer circuits and methodsALTERA CORP·Filed 2017·Granted Oct 17, 2017·0 cites·20 claims
- 0545US12125518B2Method and apparatus of receive enable margining in memory interfaceSKYECHIP SDN BHD·Filed 2022·Granted Oct 22, 2024·0 cites·4 claims
- 0645US11177806B2Techniques for reducing the effects of aging in logic circuitsINTEL CORP·Filed 2018·Granted Nov 16, 2021·0 cites·20 claims
- 0744US11349691B1Apparatus and a method for handling non-continuous data transfer for a decision feedback equalizer in a memory subsystemSKYECHIP SDN BHD·Filed 2021·Granted May 31, 2022·0 cites·6 claims
- 0842US2025240022A1Digital delay line of a memory system and method of adjusting timing of clocks using thereofSKYECHIP SDN BHD·Filed 2024·Application pending·0 cites
- 0941US11411394B2Voltage clamping circuit for protecting an internal circuitry and a method of operating thereofSKYECHIP SDN BHD·Filed 2021·Granted Aug 9, 2022·0 cites·4 claims
- 1034US10224911B1Dual signal protocol input/output (I/O) buffer circuitALTERA CORP·Filed 2016·Granted Mar 5, 2019·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →