Inventor · disambiguated record
Hong Wang
Also filed as: WANG HONG · WANG HONG QIANG
118 granted patents·23 pending applications·1,326 citations·filing 2000–2018
99Inventor score
Top patents by PatentIndex Score
141 records- 0197US7882339B2Primitives to enhance thread-level speculationINTEL CORP·Filed 2005·Granted Feb 1, 2011·56 cites·11 claims
- 0296US7437581B2Method and apparatus for varying energy per instruction according to the amount of available parallelismINTEL CORP·Filed 2004·Granted Oct 14, 2008·138 cites·50 claims
- 0394US8296743B2Compiler and runtime for heterogeneous multiprocessor systemsLINDERMAN MICHAEL D·Filed 2007·Granted Oct 23, 2012·84 cites·25 claims
- 0493US10585667B2Method and system to provide user-level multithreadingINTEL CORP·Filed 2018·Granted Mar 10, 2020·7 cites·18 claims
- 0591US8108863B2Load balancing for multi-threaded applications via asymmetric power throttlingRAKVIC RYAN·Filed 2005·Granted Jan 31, 2012·30 cites·24 claims
- 0690US8719806B2Speculative multi-threading for instruction prefetch and/or trace pre-buildWANG HONG·Filed 2010·Granted May 6, 2014·12 cites·14 claims
- 0790US8479176B2Register mapping techniques for efficient dynamic binary translationOTTONI GUILHERME D·Filed 2010·Granted Jul 2, 2013·32 cites·21 claims
- 0890US8037465B2Thread-data affinity optimization using compilerINTEL CORP·Filed 2005·Granted Oct 11, 2011·28 cites·19 claims
- 0989US8346760B2Method and apparatus to improve execution of a stored programINTEL CORP·Filed 2009·Granted Jan 1, 2013·29 cites·15 claims
- 1089US7587584B2Mechanism to exploit synchronization overhead to improve multithreaded performanceINTEL CORP·Filed 2005·Granted Sep 8, 2009·31 cites·25 claims
- 1189US7487341B2Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resourceINTEL CORP·Filed 2006·Granted Feb 3, 2009·36 cites·22 claims
- 1288US9990206B2Mechanism for instruction set based thread execution of a plurality of instruction sequencersINTEL CORP·Filed 2013·Granted Jun 5, 2018·8 cites·18 claims
- 1387US8612949B2Methods and apparatuses for compiler-creating helper threads for multi-threadingLIAO SHIH-WEI·Filed 2009·Granted Dec 17, 2013·18 cites·12 claims
- 1487US8479217B2Apparatus, system, and method for persistent user-level threadCHINYA GAUTHAM·Filed 2011·Granted Jul 2, 2013·7 cites·19 claims
- 1587US8010969B2Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencersINTEL CORP·Filed 2005·Granted Aug 30, 2011·16 cites·32 claims
- 1686US8719547B2Providing hardware support for shared virtual memory between local and remote physical memoryCHINYA GAUTHAM N·Filed 2009·Granted May 6, 2014·20 cites·29 claims
- 1786US8301868B2System to profile and optimize user software in a managed run-time environmentNEWBURN CHRIS J·Filed 2005·Granted Oct 30, 2012·15 cites·22 claims
- 1886US7882498B2Method, system, and program of a compiler to parallelize source codeINTEL CORP·Filed 2006·Granted Feb 1, 2011·18 cites·24 claims
- 1986US7849465B2Programmable event driven yield mechanism which may activate service threadsINTEL CORP·Filed 2005·Granted Dec 7, 2010·18 cites·24 claims
- 2086US7523465B2Methods and apparatus for generating speculative helper thread spawn-target pointsINTEL CORP·Filed 2003·Granted Apr 21, 2009·35 cites·31 claims
- 2185US8762694B1Programmable event-driven yield mechanismZOU XIANG·Filed 2006·Granted Jun 24, 2014·24 cites·26 claims
- 2285US7743233B2Sequencer address managementINTEL CORP·Filed 2005·Granted Jun 22, 2010·15 cites·21 claims
- 2385US6928645B2Software-based speculative pre-computation and multithreadingINTEL CORP·Filed 2001·Granted Aug 9, 2005·48 cites·16 claims
- 2483US9985661B1Reed-Solomon erasure code decoderXILINX INC·Filed 2016·Granted May 29, 2018·4 cites·20 claims
- 2583US7580914B2Method and apparatus to improve execution of a stored programINTEL CORP·Filed 2003·Granted Aug 25, 2009·33 cites·28 claims
- 2683US7020766B1Processing essential and non-essential code separatelyINTEL CORP·Filed 2000·Granted Mar 28, 2006·34 cites·37 claims
- 2782US10496413B2Efficient hardware-based extraction of program instructions for critical pathsINTEL CORP·Filed 2017·Granted Dec 3, 2019·4 cites·22 claims
- 2882US6732260B1Presbyopic branch target prefetch method and apparatusINTEL CORP·Filed 2000·Granted May 4, 2004·31 cites·30 claims
- 2981US8205200B2Compiler-based scheduling optimization hints for user-level threadsLIAO SHIH-WEI·Filed 2005·Granted Jun 19, 2012·13 cites·24 claims
- 3081US7631307B2User-programmable low-overhead multithreadingINTEL CORP·Filed 2003·Granted Dec 8, 2009·44 cites·12 claims
- 3180US7398521B2Methods and apparatuses for thread management of multi-threadingINTEL CORP·Filed 2004·Granted Jul 8, 2008·26 cites·14 claims
- 3279US9164764B2Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power modeINTEL CORP·Filed 2014·Granted Oct 20, 2015·3 cites·20 claims
- 3379US8516483B2Transparent support for operating system services for a sequestered sequencerCHINYA GAUTHAM·Filed 2005·Granted Aug 20, 2013·10 cites·26 claims
- 3479US8078831B2Method and apparatus for affinity-guided speculative helper threads in chip multiprocessorsWANG HONG·Filed 2010·Granted Dec 13, 2011·5 cites·8 claims
- 3579US7904696B2Communication paths for enabling inter-sequencer communication following lock competition and accelerator registrationINTEL CORP·Filed 2007·Granted Mar 8, 2011·7 cites·16 claims
- 3679US7487502B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2003·Granted Feb 3, 2009·19 cites·37 claims
- 3779US7404067B2Method and apparatus for efficient utilization for prescient instruction prefetchINTEL CORP·Filed 2003·Granted Jul 22, 2008·25 cites·4 claims
- 3878US9003164B2Providing hardware support for shared virtual memory between local and remote physical memoryINTEL CORP·Filed 2014·Granted Apr 7, 2015·4 cites·20 claims
- 3978US8762692B2Single instruction for specifying and saving a subset of registers, specifying a pointer to a work-monitoring function to be executed after waking, and entering a low-power modeSCHUCHMAN ETHAN·Filed 2007·Granted Jun 24, 2014·9 cites·31 claims
- 4078US7818547B2Method and apparatus for efficient resource utilization for prescient instruction prefetchINTEL CORP·Filed 2008·Granted Oct 19, 2010·7 cites·18 claims
- 4178US7810083B2Mechanism to emulate user-level multithreading on an OS-sequestered sequencerINTEL CORP·Filed 2004·Granted Oct 5, 2010·25 cites·37 claims
- 4278US7657880B2Safe store for speculative helper threadsINTEL CORP·Filed 2003·Granted Feb 2, 2010·26 cites·30 claims
- 4378US7069545B2Quantization and compression for computation reuseINTEL CORP·Filed 2000·Granted Jun 27, 2006·29 cites·31 claims
- 4477US6507895B1Method and apparatus for access demarcationINTEL CORP·Filed 2000·Granted Jan 14, 2003·25 cites·25 claims
- 4576US10846084B2Supporting timely and context triggered prefetching in microprocessorsINTEL CORP·Filed 2018·Granted Nov 24, 2020·2 cites·20 claims
- 4676US10579414B2Misprediction-triggered local history-based branch predictionINTEL CORP·Filed 2017·Granted Mar 3, 2020·2 cites·18 claims
- 4776US10459858B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2017·Granted Oct 29, 2019·1 cites·14 claims
- 4875US10877910B2Programmable event driven yield mechanism which may activate other threadsINTEL CORP·Filed 2017·Granted Dec 29, 2020·1 cites·10 claims
- 4975US10754655B2Automatic predication of hard-to-predict convergent branchesINTEL CORP·Filed 2018·Granted Aug 25, 2020·2 cites·18 claims
- 5075US10331582B2Write congestion aware bypass for non-volatile memory, last level cache (LLC) dropping from write queue responsive to write queue being full and read queue threshold wherein the threshold is derived from latency of write to LLC and main memory retrieval timeINTEL CORP·Filed 2017·Granted Jun 25, 2019·2 cites·20 claims
Showing the top 50 of 141 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →