Inventor · disambiguated record

Hsien-Wen Liu

Also filed as: LIU HSIEN-WEN

141 granted patents·54 pending applications·466 citations·filing 1999–2024

99Inventor score

Technology areasH10W H10P H10D G11C H02K

Files withTAIWAN SEMICONDUCTOR MFG CO LTD43 NANYA TECHNOLOGY CORP36 SU KUO-HUI10 HSIEH MING-TENG7 JANG JENG-HSING7

Top patents by PatentIndex Score

195 records

0197US11756928B2Multi-chip packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Sep 12, 2023·2 cites·20 claims
0297US9520372B1Wafer level package (WLP) and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Dec 13, 2016·14 cites·20 claims
0396US10763239B2Multi-chip wafer level packages and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Sep 1, 2020·13 cites·17 claims
0495US12381180B2Multi-chip packages and methods of forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Aug 5, 2025·1 cites·20 claims
0593US9881908B2Integrated fan-out package on package structure and methods of forming sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 30, 2018·11 cites·18 claims
0692US11456257B2Semiconductor package with dual sides of metal routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 27, 2022·6 cites·20 claims
0792US10867924B2Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 15, 2020·6 cites·20 claims
0892US10019350B1Dram and method for accessing a dramNANYA TECHNOLOGY CORP·Filed 2017·Granted Jul 10, 2018·14 cites·12 claims
0991US11189596B2Methods of forming multi-chip wafer level packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Nov 30, 2021·2 cites·20 claims
1091US7078761B2Nonvolatile memory solution using single-poly pFlash technologyCHINGIS TECHNOLOGY CORP·Filed 2004·Granted Jul 18, 2006·70 cites·7 claims
1190US10529671B2Package structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Jan 7, 2020·5 cites·20 claims
1290US10354988B2Using metal-containing layer to reduce carrier shock in package formationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jul 16, 2019·5 cites·20 claims
1389US10347574B2Integrated fan-out packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Jul 9, 2019·5 cites·20 claims
1489US10236035B1DRAM memory device adjustable refresh rate method to alleviate effects of row hammer eventsNANYA TECHNOLOGY CORP·Filed 2017·Granted Mar 19, 2019·9 cites·14 claims
1588US10074617B2Wafer level package (WLP) and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 11, 2018·4 cites·20 claims
1688US9595510B1Structure and formation method for chip packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Mar 14, 2017·4 cites·20 claims
1787US10510690B2Wafer level package (WLP) and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Dec 17, 2019·3 cites·20 claims
1886US10083949B2Using metal-containing layer to reduce carrier shock in package formationTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 25, 2018·4 cites·20 claims
1986US6713341B2Method of forming a bottle-shaped trench in a semiconductor substrateNANYA TECHNOLOGY CORP·Filed 2002·Granted Mar 30, 2004·38 cites·18 claims
2085US8278732B1Antifuse element for integrated circuit deviceHO JAR-MING·Filed 2011·Granted Oct 2, 2012·8 cites·10 claims
2185US7339229B2Nonvolatile memory solution using single-poly pFlash technologyCHINGIS TECHNOLOGY CORP·Filed 2006·Granted Mar 4, 2008·13 cites·4 claims
2284US8420541B2Method for increasing adhesion between polysilazane and silicon nitrideSHIH SHING-YIH·Filed 2011·Granted Apr 16, 2013·7 cites·20 claims
2384US2025105077A1Package-on-package structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
2483US10049714B1DRAM and method for managing power thereofNANYA TECHNOLOGY CORP·Filed 2017·Granted Aug 14, 2018·6 cites·8 claims
2583US8389402B2Method for via formation in a semiconductor deviceLIN CHIH CHING·Filed 2011·Granted Mar 5, 2013·6 cites·11 claims
2682US8367509B1Self-aligned method for forming contact of device with reduced step heightNANYA TECHNOLOGY CORP·Filed 2011·Granted Feb 5, 2013·7 cites·18 claims
2782US7982315B2Semiconductor structure and method of making the sameNANYA TECHNOLOGY CORP·Filed 2008·Granted Jul 19, 2011·10 cites·11 claims
2882US2024387308A1Manufacturing method of package-on-package structure and manufacturing method of integrated fan-out packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
2980US2024387297A1Semiconductor structure and test method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
3080US2024389239A1Methods and systems for improving surface mount joinderTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
3179US10879162B2Integrated fan-out packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 29, 2020·2 cites·15 claims
3279US10276228B1DRAM and method of operating the sameNANYA TECHNOLOGY CORP·Filed 2018·Granted Apr 30, 2019·4 cites·20 claims
3378US10861801B2Wafer level package (WLP) and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Dec 8, 2020·1 cites·20 claims
3478US9287221B2Method for forming crack stop structureNANYA TECHNOLOGY CORP·Filed 2015·Granted Mar 15, 2016·2 cites·7 claims
3578US8431933B2Memory layout structure and memory structureLEE TZUNG-HAN·Filed 2010·Granted Apr 30, 2013·5 cites·9 claims
3678US8252684B1Method of forming a trench by a silicon-containing maskLEE HSIU-CHUN·Filed 2011·Granted Aug 28, 2012·6 cites·7 claims
3778US6727159B2Method of forming a shallow trench isolation in a semiconductor substrateNANYA TECHNOLOGY CORP·Filed 2002·Granted Apr 27, 2004·23 cites·7 claims
3877US12205853B2Integrated circuit test method and structure thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jan 21, 2025·0 cites·20 claims
3975US12382587B2Methods and systems for improving surface mount joinderTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Aug 5, 2025·0 cites·20 claims
4075US6426271B2Method of rounding the corner of a shallow trench isolation regionNANYA TECHNOLOGY CORP·Filed 2001·Granted Jul 30, 2002·17 cites·20 claims
4174US12113025B2Semiconductor package with dual sides of metal routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Oct 8, 2024·0 cites·20 claims
4274US9531056B2Patch antenna and wireless communication device using the sameSERCOMM CORP·Filed 2014·Granted Dec 27, 2016·3 cites·21 claims
4374US8288279B1Method for forming conductive contactHO JAR-MING·Filed 2011·Granted Oct 16, 2012·4 cites·10 claims
4474US8178418B1Method for fabricating intra-device isolation structureHO JAR-MING·Filed 2011·Granted May 15, 2012·3 cites·10 claims
4573US12198996B2Integrated fan-out package, package-on-package structure, and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 14, 2025·0 cites·20 claims
4673US11342306B2Multi-chip wafer level packagesTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 24, 2022·0 cites·20 claims
4773US11329031B2Structure and formation method for chip packageTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted May 10, 2022·0 cites·20 claims
4873US10269445B1Memory device and operating method thereofNANYA TECHNOLOGY CORP·Filed 2017·Granted Apr 23, 2019·3 cites·14 claims
4973US8486834B2Method for manufacturing memory deviceHSU PING·Filed 2011·Granted Jul 16, 2013·4 cites·7 claims
5073US6716696B2Method of forming a bottle-shaped trench in a semiconductor substrateNANYA TECHNOLOGY CORP·Filed 2002·Granted Apr 6, 2004·18 cites·10 claims

Showing the top 50 of 195 patent records by PatentIndex Score.

Join the waitlist — get patent alerts

Get an alert when Hsien-Wen Liu files or is granted a new patent.

We store only your email — no account needed. See our privacy policy.

Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →