Inventor · disambiguated record
Hsiao-Han Thio
Also filed as: THIO HSIAO · THIO HSIAO H · THIO HSIAO-HAN
16 granted patents·2 pending applications·199 citations·filing 2002–2013
93Inventor score
Top patents by PatentIndex Score
18 records- 0196US8832507B2Systems and methods for generating dynamic super blocksPOST DANIEL J·Filed 2010·Granted Sep 9, 2014·33 cites·25 claims
- 0293US6461905B1Dummy gate process to reduce the Vss resistance of flash productsADVANCED MICRO DEVICES INC·Filed 2002·Granted Oct 8, 2002·80 cites·25 claims
- 0389US8503257B2Read disturb scorecardPOST DANIEL J·Filed 2010·Granted Aug 6, 2013·13 cites·27 claims
- 0489US8367493B1Void free interlayer dielectricSPANSION LLC·Filed 2005·Granted Feb 5, 2013·17 cites·17 claims
- 0586US8370603B2Architecture for address mapping of managed non-volatile memoryAPPLE INC·Filed 2009·Granted Feb 5, 2013·13 cites·18 claims
- 0666US6696331B1Method of protecting a stacked gate structure during fabricationADVANCED MICRO DEVICES INC·Filed 2002·Granted Feb 24, 2004·12 cites·38 claims
- 0765US6670227B1Method for fabricating devices in core and periphery semiconductor regions using dual spacersADVANCED MICRO DEVICES INC·Filed 2003·Granted Dec 30, 2003·15 cites·17 claims
- 0864US8862851B2Architecture for address mapping of managed non-volatile memoryAPPLE INC·Filed 2012·Granted Oct 14, 2014·1 cites·15 claims
- 0956US6808945B1Method and system for testing tunnel oxide on a memory-related structureADVANCED MICRO DEVICES INC·Filed 2003·Granted Oct 26, 2004·5 cites·25 claims
- 1053US8319266B1Etch stop layer for memory cell reliability improvementKINOSHITA HIROYUKI·Filed 2004·Granted Nov 27, 2012·3 cites·14 claims
- 1153US2014112079A1Controlling and staggering operations to limit current spikesAPPLE INC·Filed 2013·Application pending·0 cites
- 1252US8614475B2Void free interlayer dielectricSPANSION LLC·Filed 2012·Granted Dec 24, 2013·0 cites·20 claims
- 1352US6716710B1Using a first liner layer as a spacer in a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2002·Granted Apr 6, 2004·5 cites·6 claims
- 1451US8658496B2Etch stop layer for memory cell reliability improvementKINOSHITA HIROYUKI·Filed 2012·Granted Feb 25, 2014·0 cites·20 claims
- 1545US6689666B1Replacing a first liner layer with a thicker oxide layer when forming a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2002·Granted Feb 10, 2004·2 cites·20 claims
- 1645US2011173462A1Controlling and staggering operations to limit current spikesAPPLE INC·Filed 2010·Application pending·0 cites
- 1742US7939440B2Junction leakage suppression in memory devicesSPANSION LLC·Filed 2005·Granted May 10, 2011·0 cites·18 claims
- 1836US8536011B2Junction leakage suppression in memory devicesAHMED SHIBLY S·Filed 2011·Granted Sep 17, 2013·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →