Inventor · disambiguated record
Hsu Kai Yang
Also filed as: YANG HSU KAI · YANG HSU KAI KARL
33 granted patents·3 pending applications·450 citations·filing 1998–2024
97Inventor score
Files withMAGIC TECHNOLOGIES INC18YANG HSU KAI7APPLIED SPINTRONICS INC4HEADWAY TECHNOLOGIES INC3KAITECH ENGINEERING INC2
Top patents by PatentIndex Score
36 records- 0196US7852662B2Spin-torque MRAM: spin-RAM, arrayMAGIC TECHNOLOGIES INC·Filed 2007·Granted Dec 14, 2010·56 cites·35 claims
- 0293US7782661B2Boosted gate voltage programming for spin-torque MRAM arrayMAGIC TECHNOLOGIES INC·Filed 2008·Granted Aug 24, 2010·26 cites·30 claims
- 0391US7184302B2Highly efficient segmented word line MRAM arrayAPPLIED SPINTRONICS INC·Filed 2005·Granted Feb 27, 2007·28 cites·20 claims
- 0490US7499314B2Reference cell scheme for MRAMMAGIC TECHNOLOGIES INC·Filed 2007·Granted Mar 3, 2009·21 cites·8 claims
- 0588US6392427B1Testing electronic devicesKAITECH ENGINEERING INC·Filed 1998·Granted May 21, 2002·103 cites·24 claims
- 0686US9170879B2Method and apparatus for scrubbing accumulated data errors from a memory systemYANG HSU KAI·Filed 2009·Granted Oct 27, 2015·17 cites·49 claims
- 0786US7362644B2Configurable MRAM and method of configurationMAGIC TECHNOLOGIES INC·Filed 2005·Granted Apr 22, 2008·17 cites·33 claims
- 0885US7321507B2Reference cell scheme for MRAMMAGIC TECHNOLOGIES INC·Filed 2005·Granted Jan 22, 2008·14 cites·67 claims
- 0984US6295226B1Memory device having enhanced programming and/or erase characteristicsKAITECH ENGINEERING INC·Filed 2000·Granted Sep 25, 2001·37 cites·43 claims
- 1083US7480172B2Programming scheme for segmented word line MRAM arrayMAGIC TECHNOLOGIES INC·Filed 2006·Granted Jan 20, 2009·15 cites·25 claims
- 1180US8775865B2Method and apparatus for scrubbing accumulated disturb data errors in an array of SMT MRAM memory cells including rewriting reference bitsYANG HSU KAI·Filed 2011·Granted Jul 8, 2014·6 cites·37 claims
- 1280US7613868B2Method and system for optimizing the number of word line segments in a segmented MRAM arrayHEADWAY TECHNOLOGIES INC·Filed 2004·Granted Nov 3, 2009·28 cites·10 claims
- 1379US8274819B2Read disturb free SMT MRAM reference cell circuitYANG HSU KAI·Filed 2010·Granted Sep 25, 2012·7 cites·12 claims
- 1475US12153085B2Massively independent testers systemYANG HSU KAI·Filed 2024·Granted Nov 26, 2024·0 cites·20 claims
- 1575US8570793B1Shared bit line SMT MRAM array with shunting transistors between bit linesMAGIC TECHNOLOGIES INC·Filed 2013·Granted Oct 29, 2013·3 cites·3 claims
- 1674US7977111B2Devices using addressable magnetic tunnel junction array to detect magnetic particlesMAGIC TECHNOLOGIES INC·Filed 2008·Granted Jul 12, 2011·7 cites·42 claims
- 1772US7224628B2Adaptive algorithm for MRAM manufacturingAPPLIED SPINTRONICS INC·Filed 2006·Granted May 29, 2007·6 cites·21 claims
- 1872US7085183B2Adaptive algorithm for MRAM manufacturingAPPLIED SPINTRONICS INC·Filed 2004·Granted Aug 1, 2006·14 cites·12 claims
- 1972US6977838B1Method and system for providing a programmable current source for a magnetic memoryHEADWAY TECHNOLOGIES·Filed 2004·Granted Dec 20, 2005·20 cites·17 claims
- 2070US8018758B2Gate drive voltage boost schemes for memory arrayMAGIC TECHNOLOGIES INC·Filed 2009·Granted Sep 13, 2011·7 cites·20 claims
- 2169US8654577B2Shared bit line SMT MRAM array with shunting transistors between bit linesMAGIC TECHNOLOGIES INC·Filed 2013·Granted Feb 18, 2014·2 cites·2 claims
- 2264US7369430B2Adaptive algorithm for MRAM manufacturingHEADWAY TECHNOLOGIES INC·Filed 2006·Granted May 6, 2008·4 cites·2 claims
- 2359US8437181B2Shared bit line SMT MRAM array with shunting transistors between the bit linesYANG HSU KAI·Filed 2010·Granted May 7, 2013·1 cites·7 claims
- 2455US7609543B2Method and implementation of stress test for MRAMMAGIC TECHNOLOGIES INC·Filed 2007·Granted Oct 27, 2009·3 cites·29 claims
- 2555US7321519B2Adaptive algorithm for MRAM manufacturingHEADWAY TECHNOLOGIES INC·Filed 2006·Granted Jan 22, 2008·2 cites·6 claims
- 2654US8248841B2Boosted gate voltage programming for spin-torque MRAM arrayYANG HSU KAI·Filed 2010·Granted Aug 21, 2012·1 cites·34 claims
- 2751US7957183B2Single bit line SMT MRAM array architecture and the programming methodMAGIC TECHNOLOGIES INC·Filed 2009·Granted Jun 7, 2011·2 cites·32 claims
- 2849US8576618B2Shared bit line SMT MRAM array with shunting transistors between bit linesMAGIC TECHNOLOGIES INC·Filed 2013·Granted Nov 5, 2013·0 cites·3 claims
- 2949US8565014B2Shared bit line SMT MRAM array with shunting transistors between bit linesMAGIC TECHNOLOGIES INC·Filed 2013·Granted Oct 22, 2013·0 cites·5 claims
- 3049US2010153633A1PC architecture using fast NV RAM in main memoryMAGIC TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
- 3147US7986572B2Magnetic memory capable of minimizing gate voltage stress in unselected memory cellsMAGIC TECHNOLOGIES INC·Filed 2009·Granted Jul 26, 2011·1 cites·20 claims
- 3245US7180769B2World line segment select transistor on word line current source sideAPPLIED SPINTRONICS INC·Filed 2005·Granted Feb 20, 2007·2 cites·14 claims
- 3344US2010191896A1Solid state drive controller with fast NVRAM buffer and non-volatile tablesMAGIC TECHNOLOGIES INC·Filed 2009·Application pending·0 cites
- 3442US11396106B2Hair cutting device adapted for cutting one's own hairYANG HSU KAI·Filed 2021·Granted Jul 26, 2022·0 cites·5 claims
- 3538US2010302838A1Read disturb-free SMT reference cell schemeMAGIC TECHNOLOGIES INC·Filed 2009·Application pending·0 cites
- 3634US7027324B2Method and system for providing common read and write word lines for a segmented word line MRAM arrayAPPLIED SPINTRONICS TECH INC·Filed 2004·Granted Apr 11, 2006·0 cites·21 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →