Inventor · disambiguated record
Huang-Yu Chen
Also filed as: CHEN HUANG -YU
56 granted patents·8 pending applications·371 citations·filing 2009–2025
98Inventor score
Files withTAIWAN SEMICONDUCTOR MFG CO LTD36TAIWAN SEMICONDUCTOR MFG11CHEN HUANG-YU9HSIEH KEN-HSIEN1HSU CHIN-HSIUNG1
Top patents by PatentIndex Score
64 records- 0198US11715733B2Integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Aug 1, 2023·4 cites·20 claims
- 0297US8584052B2Cell layout for multiple patterning technologyCHEN HUANG-YU·Filed 2011·Granted Nov 12, 2013·26 cites·19 claims
- 0397US8448100B1Tool and method for eliminating multi-patterning conflictsLIN HUNG LUNG·Filed 2012·Granted May 21, 2013·102 cites·18 claims
- 0495US8601409B1Compression method and system for use with multi-patterningCHEN HUANG-YU·Filed 2012·Granted Dec 3, 2013·30 cites·21 claims
- 0594US10162925B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Dec 25, 2018·10 cites·20 claims
- 0693US8418111B2Method and apparatus for achieving multiple patterning technology compliant design layoutCHEN HUANG-YU·Filed 2010·Granted Apr 9, 2013·29 cites·28 claims
- 0792US8813016B1Multiple via connections using connectivity ringsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 19, 2014·15 cites·20 claims
- 0891US8694945B2Automatic place and route method for electromigration tolerant power distributionWANG CHUNG-HSING·Filed 2011·Granted Apr 8, 2014·13 cites·13 claims
- 0991US8239806B2Routing system and method for double patterning technologyCHEN HUANG-YU·Filed 2009·Granted Aug 7, 2012·27 cites·19 claims
- 1090US11669669B2Circuit layouts and related methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Jun 6, 2023·2 cites·20 claims
- 1190US11620426B2Automated system and method for circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Apr 4, 2023·2 cites·20 claims
- 1290US8799834B1Self-aligned multiple patterning layout designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Aug 5, 2014·15 cites·20 claims
- 1390US8745556B2Layout method and system for multi-patterning integrated circuitsCHEN HUANG-YU·Filed 2012·Granted Jun 3, 2014·12 cites·22 claims
- 1489US8683392B2Double patterning methodologyHSIEH KEN-HSIEN·Filed 2011·Granted Mar 25, 2014·11 cites·17 claims
- 1589US8365102B2Method for checking and fixing double-patterning layoutTAIWAN SEMICONDUCTOR MFG·Filed 2010·Granted Jan 29, 2013·6 cites·21 claims
- 1688US12001773B2Automated system and method for circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 4, 2024·1 cites·20 claims
- 1787US9380709B2Method of cutting conductive patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jun 28, 2016·5 cites·18 claims
- 1884US11568119B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jan 31, 2023·1 cites·20 claims
- 1984US11501052B1Conductor scheme selection and track planning for mixed-diagonal-Manhattan routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Nov 15, 2022·1 cites·20 claims
- 2084US8977991B2Method and system for replacing a pattern in a layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Mar 10, 2015·6 cites·20 claims
- 2183US10922466B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2018·Granted Feb 16, 2021·2 cites·20 claims
- 2283US8914755B1Layout re-decomposition for multiple patterning layoutsTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Dec 16, 2014·7 cites·20 claims
- 2383US8601408B2Method and system for replacing a pattern in a layoutCHEN HUANG-YU·Filed 2011·Granted Dec 3, 2013·6 cites·19 claims
- 2482US9317650B2Double patterning technology (DPT) layout routingTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Apr 19, 2016·5 cites·20 claims
- 2582US8453095B2Systems and methods for creating frequency-dependent netlistSU KE-YING·Filed 2011·Granted May 28, 2013·7 cites·20 claims
- 2681US12336295B2Integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jun 17, 2025·0 cites·20 claims
- 2781US12013643B2Method of cutting conductive patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jun 18, 2024·0 cites·20 claims
- 2881US11907007B2Clock signal distribution system, integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 20, 2024·1 cites·20 claims
- 2981US8211807B2Double patterning technology using single-patterning-spacer-techniqueCHEN HUANG-YU·Filed 2010·Granted Jul 3, 2012·5 cites·10 claims
- 3081US2025287698A1Integrated circuit device and non-transitory computer-readable recording medium storing cell layout for integrated circuit deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3179US12367333B2Automated system and method for circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Jul 22, 2025·0 cites·20 claims
- 3279US12039251B2Cell layout of semiconductor deviceTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Granted Jul 16, 2024·0 cites·20 claims
- 3377US9213795B2Multiple via connections using connectivity ringsTAIWAN SEMICONDUCTOR MFG·Filed 2014·Granted Dec 15, 2015·3 cites·20 claims
- 3477US8898608B1Method for displaying timing information of an integrated circuit floorplanTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 25, 2014·3 cites·20 claims
- 3577US2025298770A1Diagonal torus networkTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 3676US2024160826A1Conductor scheme selection and track planning for mixed-diagonal-manhattan routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2023·Application pending·0 cites
- 3775US11861284B2Conductor scheme selection and track planning for mixed-diagonal-manhattan routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2022·Granted Jan 2, 2024·0 cites·20 claims
- 3875US8898600B2Layout optimization for integrated designTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Nov 25, 2014·3 cites·19 claims
- 3973US2024201727A1Clock signal distribution system, integrated circuit device and methodTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Application pending·0 cites
- 4071US9418196B2Layout optimization for integrated circuit designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 16, 2016·1 cites·20 claims
- 4171US9026953B2Compression method and system for use with multi-patterningTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted May 5, 2015·1 cites·20 claims
- 4270US8875067B2Reusable cut mask for multiple layersTAIWAN SEMICONDUCTOR MFG·Filed 2013·Granted Oct 28, 2014·2 cites·20 claims
- 4369US9594866B2Method for checking and fixing double-patterning layoutTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2012·Granted Mar 14, 2017·2 cites·20 claims
- 4468US8418117B2Chip-level ECO shrinkCHEN HUANG-YU·Filed 2010·Granted Apr 9, 2013·2 cites·26 claims
- 4567US11429028B2Method of cutting conductive patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Aug 30, 2022·0 cites·19 claims
- 4666US9471742B2Method for displaying timing information of an integrated circuit floorplan in real timeTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Oct 18, 2016·1 cites·20 claims
- 4765US9384307B2Stitch and trim methods for double patterning compliant standard cell designTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 5, 2016·1 cites·20 claims
- 4864US12346285B2Diagonal torus networkTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Jul 1, 2025·0 cites·20 claims
- 4962US9893009B2Duplicate layering and routingTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2014·Granted Feb 13, 2018·1 cites·20 claims
- 5059US10509322B2Method of cutting conductive patternsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Dec 17, 2019·0 cites·21 claims
Showing the top 50 of 64 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →