Inventor · disambiguated record
Huajie Chen
Also filed as: CHEN HUAJIE
62 granted patents·9 pending applications·1,526 citations·filing 2002–2019
99Inventor score
Top patents by PatentIndex Score
71 records- 0198US7859013B2Metal oxide field effect transistor with a sharp haloIBM·Filed 2007·Granted Dec 28, 2010·100 cites·17 claims
- 0298US6891192B2Structure and method of making strained semiconductor CMOS transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2003·Granted May 10, 2005·179 cites·11 claims
- 0397US6916698B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2004·Granted Jul 12, 2005·139 cites·8 claims
- 0496US7176481B2In situ doped embedded sige extension and source/drain for enhanced PFET performanceIBM·Filed 2005·Granted Feb 13, 2007·52 cites·28 claims
- 0596US7071103B2Chemical treatment to retard diffusion in a semiconductor overlayerIBM·Filed 2004·Granted Jul 4, 2006·120 cites·25 claims
- 0695US7381623B1Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performanceIBM·Filed 2007·Granted Jun 3, 2008·31 cites·16 claims
- 0795US6958286B2Method of preventing surface roughening during hydrogen prebake of SiGe substratesIBM·Filed 2004·Granted Oct 25, 2005·238 cites·20 claims
- 0894US7781800B2Embedded silicon germanium using a double buried oxide silicon-on-insulator waferIBM·Filed 2008·Granted Aug 24, 2010·24 cites·17 claims
- 0993US7303949B2High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufactureIBM·Filed 2003·Granted Dec 4, 2007·44 cites·3 claims
- 1093US6762469B2High performance CMOS device structure with mid-gap metal gateIBM·Filed 2002·Granted Jul 13, 2004·68 cites·5 claims
- 1192US7291528B2Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2005·Granted Nov 6, 2007·16 cites·17 claims
- 1291US6906360B2Structure and method of making strained channel CMOS transistors having lattice-mismatched epitaxial extension and source and drain regionsIBM·Filed 2003·Granted Jun 14, 2005·55 cites·12 claims
- 1391US6893936B1Method of Forming strained SI/SIGE on insulator with silicon germanium bufferIBM·Filed 2004·Granted May 17, 2005·65 cites·20 claims
- 1490US7271043B2Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levelsIBM·Filed 2005·Granted Sep 18, 2007·17 cites·26 claims
- 1589US7396714B2Method of making strained semiconductor transistors having lattice-mismatched semiconductor regions underlying source and drain regionsIBM·Filed 2007·Granted Jul 8, 2008·11 cites·17 claims
- 1689US7135724B2Structure and method for making strained channel field effect transistor using sacrificial spacerIBM·Filed 2004·Granted Nov 14, 2006·47 cites·16 claims
- 1788US7297583B2Method of making strained channel CMOS transistors having lattice-mismatched epitaxialIBM·Filed 2005·Granted Nov 20, 2007·13 cites·20 claims
- 1887US9515526B2Motor and rotor thereofHUANG HUI·Filed 2011·Granted Dec 6, 2016·9 cites·7 claims
- 1986US9502930B2Motor rotor and motor having sameHUANG HUI·Filed 2011·Granted Nov 22, 2016·8 cites·7 claims
- 2085US7476580B2Structures and methods for manufacturing of dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineering with SiGe and/or Si:CIBM·Filed 2007·Granted Jan 13, 2009·9 cites·17 claims
- 2184US7446350B2Embedded silicon germanium using a double buried oxide silicon-on-insulator waferIBM·Filed 2005·Granted Nov 4, 2008·9 cites·18 claims
- 2284US7220626B2Structure and method for manufacturing planar strained Si/SiGe substrate with multiple orientations and different stress levelsIBM·Filed 2005·Granted May 22, 2007·10 cites·16 claims
- 2382US9502934B2Motor rotor and motor having sameHUANG HUI·Filed 2011·Granted Nov 22, 2016·6 cites·15 claims
- 2482US7452761B2Hybrid SOI-bulk semiconductor transistorsIBM·Filed 2007·Granted Nov 18, 2008·7 cites·4 claims
- 2580US6777302B1Nitride pedestal for raised extrinsic base HBT processIBM·Filed 2003·Granted Aug 17, 2004·27 cites·20 claims
- 2679US7645656B2Structure and method for making strained channel field effect transistor using sacrificial spacerIBM·Filed 2006·Granted Jan 12, 2010·7 cites·18 claims
- 2779US6924517B2Thin channel FET with recessed source/drains and extensionsIBM·Filed 2003·Granted Aug 2, 2005·23 cites·28 claims
- 2878US7767503B2Hybrid SOI/bulk semiconductor transistorsIBM·Filed 2008·Granted Aug 3, 2010·5 cites·7 claims
- 2978US6780695B1BiCMOS integration scheme with raised extrinsic baseIBM·Filed 2003·Granted Aug 24, 2004·24 cites·17 claims
- 3076US7309660B2Buffer layer for selective SiGe growth for uniform nucleationIBM·Filed 2004·Granted Dec 18, 2007·17 cites·19 claims
- 3176US6989058B2Use of thin SOI to inhibit relaxation of SiGe layersIBM·Filed 2003·Granted Jan 24, 2006·15 cites·30 claims
- 3275US8168489B2High performance stress-enhanced MOSFETS using Si:C and SiGe epitaxial source/drain and method of manufactureCHEN HUAJIE·Filed 2007·Granted May 1, 2012·3 cites·17 claims
- 3375US6749684B1Method for improving CVD film quality utilizing polysilicon gettererIBM·Filed 2003·Granted Jun 15, 2004·11 cites·19 claims
- 3473US7723791B2Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levelsIBM·Filed 2008·Granted May 25, 2010·4 cites·10 claims
- 3573US6972247B2Method of fabricating strained Si SOI wafersIBM·Filed 2003·Granted Dec 6, 2005·15 cites·67 claims
- 3672US7679141B2High-quality SGOI by annealing near the alloy melting pointIBM·Filed 2008·Granted Mar 16, 2010·3 cites·19 claims
- 3771US7816664B2Defect reduction by oxidation of siliconIBM·Filed 2008·Granted Oct 19, 2010·3 cites·11 claims
- 3870US7750414B2Structure and method for reducing threshold voltage variationIBM·Filed 2008·Granted Jul 6, 2010·4 cites·2 claims
- 3969US7682915B2Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performanceIBM·Filed 2008·Granted Mar 23, 2010·3 cites·17 claims
- 4068US7384835B2Metal oxide field effect transistor with a sharp halo and a method of forming the transistorIBM·Filed 2006·Granted Jun 10, 2008·3 cites·16 claims
- 4168US7348253B2High-quality SGOI by annealing near the alloy melting pointIBM·Filed 2004·Granted Mar 25, 2008·10 cites·13 claims
- 4267US7026249B2SiGe lattice engineering using a combination of oxidation, thinning and epitaxial regrowthIBM·Filed 2003·Granted Apr 11, 2006·11 cites·15 claims
- 4366US7507988B2Semiconductor heterostructure including a substantially relaxed, low defect density SiGe layerIBM·Filed 2007·Granted Mar 24, 2009·2 cites·1 claims
- 4466US7423303B2Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levelsIBM·Filed 2007·Granted Sep 9, 2008·2 cites·9 claims
- 4565US8901566B2High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufactureCHEN HUAJIE·Filed 2007·Granted Dec 2, 2014·1 cites·17 claims
- 4664US7550370B2Method of forming thin SGOI wafers with high relaxation and low stacking fault defect densityIBM·Filed 2004·Granted Jun 23, 2009·11 cites·11 claims
- 4764US7504693B2Dislocation free stressed channels in bulk silicon and SOI CMOS devices by gate stress engineeringIBM·Filed 2004·Granted Mar 17, 2009·8 cites·13 claims
- 4864US7247546B2Method of forming strained silicon materials with improved thermal conductivityIBM·Filed 2004·Granted Jul 24, 2007·9 cites·17 claims
- 4961US9401424B2High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufactureSAMSUNG ELECTRONICS CO LTD·Filed 2014·Granted Jul 26, 2016·0 cites·18 claims
- 5061US7863197B2Method of forming a cross-section hourglass shaped channel region for charge carrier mobility modificationIBM·Filed 2006·Granted Jan 4, 2011·2 cites·9 claims
Showing the top 50 of 71 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →