Inventor · disambiguated record
Hung-Yu Chiu
Also filed as: CHIU HUNG-YU
13 granted patents·3 pending applications·78 citations·filing 2000–2015
89Inventor score
Top patents by PatentIndex Score
16 records- 0184US6746968B1Method of reducing charge loss for nonvolatile memoryMACRONIX INT CO LTD·Filed 2003·Granted Jun 8, 2004·32 cites·9 claims
- 0277US6562682B1Method for forming gateMACRONIX INT CO LTD·Filed 2002·Granted May 13, 2003·23 cites·20 claims
- 0359US7012004B2Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereofMACRONIX INT CO LTD·Filed 2005·Granted Mar 14, 2006·3 cites·10 claims
- 0458US6960506B2Method of fabricating a memory device having a self-aligned contactMACRONIX INT CO LTD·Filed 2003·Granted Nov 1, 2005·8 cites·21 claims
- 0553US6521518B1Method of eliminating weakness caused by high density plasma dielectric layerMACRONIX INT CO LTD·Filed 2001·Granted Feb 18, 2003·4 cites·20 claims
- 0649US6734098B2Method for fabricating cobalt salicide contactMACRONIX INT CO LTD·Filed 2002·Granted May 11, 2004·4 cites·13 claims
- 0747US9666588B2Damascene non-volatile memory cells and methods for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 30, 2017·0 cites·18 claims
- 0843US9076727B2Damascene non-volatile memory cells and methods for forming the sameCHIU HUNG-YU·Filed 2012·Granted Jul 7, 2015·0 cites·17 claims
- 0943US7157360B2Memory device and method for forming a passivation layer thereonMACRONIX INT CO LTD·Filed 2003·Granted Jan 2, 2007·2 cites·11 claims
- 1042US9082617B2Integrated circuit and fabricating method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 14, 2015·0 cites·20 claims
- 1141US6867466B2Memory device and method for forming a passivation layer thereonMACRONIX INT CO LTD·Filed 2002·Granted Mar 15, 2005·1 cites·11 claims
- 1239US6916736B2Method of forming an intermetal dielectric layerMACRONIX INT CO LTD·Filed 2003·Granted Jul 12, 2005·1 cites·12 claims
- 1336US6680256B2Process for planarization of flash memory cellMACRONIX INT CO LTD·Filed 2001·Granted Jan 20, 2004·0 cites·11 claims
- 1435US2002072217A1Method for improving contact reliability in semiconductor devicesMACRONIX INT CO LTD·Filed 2000·Application pending·0 cites
- 1532US2013178068A1Dual damascene process and apparatusYEN CHAI DER·Filed 2012·Application pending·0 cites
- 1631US2003181053A1Method of manufacturing a nonvolatile memory cell with triple spacers and the structure thereofFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →