Inventor · disambiguated record
Hung-Che Liao
Also filed as: LIAO HUNG-CHE
20 granted patents·2 pending applications·142 citations·filing 1997–2025
92Inventor score
Top patents by PatentIndex Score
22 records- 0191US6590295B1Microelectronic device with a spacer redistribution layer via and method of making the sameTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Jul 8, 2003·112 cites·10 claims
- 0291US2025365949A1Semiconductor device having non-continuous wall structure surrounding stacked gate structure including conductive layer disposed between segmented portions of the wall structure and manufacturing method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2025·Application pending·0 cites
- 0387US12464714B2Semiconductor device having non-continuous wall structure surrounding a stacked gate structure including a conductive layer disposed between segmented portions of the wall structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2024·Granted Nov 4, 2025·0 cites·20 claims
- 0474US9825046B2Flash memory device having high coupling ratioTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Nov 21, 2017·2 cites·19 claims
- 0572US11594449B2Method of making a semiconductor structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2021·Granted Feb 28, 2023·0 cites·20 claims
- 0671US11925017B2Semiconductor device having a wall structure surrounding a stacked gate structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2020·Granted Mar 5, 2024·0 cites·20 claims
- 0761US11121141B2Semiconductor structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2019·Granted Sep 14, 2021·0 cites·20 claims
- 0858US10964589B2Semiconductor structureTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted Mar 30, 2021·0 cites·20 claims
- 0957US10535670B2Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Jan 14, 2020·0 cites·20 claims
- 1057US10283510B2Semiconductor structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2017·Granted May 7, 2019·0 cites·24 claims
- 1155US9735049B2Method for fabricating semiconductor structure with passivation sidewall blockTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 15, 2017·0 cites·20 claims
- 1254US9768182B2Semiconductor structure and method for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted Sep 19, 2017·0 cites·20 claims
- 1348US5923988ATwo step thermal treatment procedure applied to polycide structures deposited using dichlorosilane as a reactantTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jul 13, 1999·14 cites·21 claims
- 1447US9666588B2Damascene non-volatile memory cells and methods for forming the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 30, 2017·0 cites·18 claims
- 1543US9076727B2Damascene non-volatile memory cells and methods for forming the sameCHIU HUNG-YU·Filed 2012·Granted Jul 7, 2015·0 cites·17 claims
- 1643US6310397B1Butted contact resistance of an SRAM by double VCC implantationTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Oct 30, 2001·8 cites·3 claims
- 1742US9082617B2Integrated circuit and fabricating method thereofTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Jul 14, 2015·0 cites·20 claims
- 1839US9449976B2Semiconductor device structure and method for manufacturing the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2013·Granted Sep 20, 2016·0 cites·19 claims
- 1936US10283604B2Contact structure for high aspect ratio and method of fabricating the sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted May 7, 2019·0 cites·20 claims
- 2033US6057186AMethod for improving the butted contact resistance of an SRAM by double Vcc implantationTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 2, 2000·4 cites·8 claims
- 2132US2013178068A1Dual damascene process and apparatusYEN CHAI DER·Filed 2012·Application pending·0 cites
- 2231US6017828AMethod for preventing backside polysilicon peeling in a 4T+2R SRAM processTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Jan 25, 2000·2 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →