Inventor · disambiguated record
Hui Jae Yoo
Also filed as: YOO HUI JAE
75 granted patents·23 pending applications·185 citations·filing 2007–2025
98Inventor score
Top patents by PatentIndex Score
98 records- 0198US11444024B2Subtractively patterned interconnect structures for integrated circuitsINTEL CORP·Filed 2020·Granted Sep 13, 2022·10 cites·30 claims
- 0296US11996411B2Stacked forksheet transistorsINTEL CORP·Filed 2020·Granted May 28, 2024·4 cites·21 claims
- 0396US11437283B2Backside contacts for semiconductor devicesINTEL CORP·Filed 2019·Granted Sep 6, 2022·12 cites·25 claims
- 0496US9793163B2Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnectsINTEL CORP·Filed 2013·Granted Oct 17, 2017·28 cites·11 claims
- 0595US12027458B2Subtractively patterned interconnect structures for integrated circuitsINTEL CORP·Filed 2022·Granted Jul 2, 2024·2 cites·20 claims
- 0695US9754821B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2016·Granted Sep 5, 2017·9 cites·10 claims
- 0795US9330963B2Conformal low temperature hermetic dielectric diffusion barriersKING SEAN·Filed 2011·Granted May 3, 2016·23 cites·10 claims
- 0894US12148734B2Transistors, memory cells, and arrangements thereofINTEL CORP·Filed 2020·Granted Nov 19, 2024·3 cites·20 claims
- 0994US9391019B2Scalable interconnect structures with selective via postsINTEL CORP·Filed 2014·Granted Jul 12, 2016·26 cites·19 claims
- 1092US9691657B2Interconnect wires including relatively low resistivity coresINTEL CORP·Filed 2016·Granted Jun 27, 2017·6 cites·9 claims
- 1191US9165824B2Interconnects with fully clad linesINTEL CORP·Filed 2013·Granted Oct 20, 2015·11 cites·19 claims
- 1290US12300537B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2024·Granted May 13, 2025·0 cites·20 claims
- 1389US12080605B2Backside contacts for semiconductor devicesINTEL CORP·Filed 2022·Granted Sep 3, 2024·1 cites·24 claims
- 1487US9935002B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2017·Granted Apr 3, 2018·2 cites·20 claims
- 1587US8461683B2Self-forming, self-aligned barriers for back-end interconnects and methods of making sameYOO HUI JAE·Filed 2011·Granted Jun 11, 2013·9 cites·17 claims
- 1686US12266568B2Interconnect wires including relatively low resistivity coresINTEL CORP·Filed 2023·Granted Apr 1, 2025·0 cites·18 claims
- 1786US12040226B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2023·Granted Jul 16, 2024·0 cites·10 claims
- 1886US11367749B2Spin orbit torque (SOT) memory devices and their methods of fabricationINTEL CORP·Filed 2018·Granted Jun 21, 2022·3 cites·14 claims
- 1986US8039920B1Methods for forming planarized hermetic barrier layers and structures formed therebyINTEL CORP·Filed 2010·Granted Oct 18, 2011·7 cites·8 claims
- 2085US8975138B2Method of creating a maskless air gap in back end interconnects with double self-aligned viasCHANDHOK MANISH·Filed 2013·Granted Mar 10, 2015·9 cites·14 claims
- 2185US2025285917A1Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2025·Application pending·0 cites
- 2283US12482744B2Subtractively patterned interconnect structures for integrated circuitsINTEL CORP·Filed 2024·Granted Nov 25, 2025·0 cites·19 claims
- 2383US12148806B2Stacked source-drain-gate connection and process for forming suchINTEL CORP·Filed 2024·Granted Nov 19, 2024·0 cites·20 claims
- 2483US11670545B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2022·Granted Jun 6, 2023·0 cites·20 claims
- 2582US11881432B2Interconnect wires including relatively low resistivity coresINTEL CORP·Filed 2022·Granted Jan 23, 2024·0 cites·20 claims
- 2682US10256141B2Maskless air gap to prevent via punch throughINTEL CORP·Filed 2015·Granted Apr 9, 2019·3 cites·20 claims
- 2782US2024203786A1Self-forming, self-aligned barriers for back-end interconnects and methods of making sameTAHOE RES LTD·Filed 2024·Application pending·0 cites
- 2882US2025201629A1Interconnect wires including relatively low resistivity coresINTEL CORP·Filed 2025·Application pending·0 cites
- 2981US11955560B2Passivation layers for thin film transistors and methods of fabricationINTEL CORP·Filed 2020·Granted Apr 9, 2024·1 cites·20 claims
- 3081US11764263B2Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approachesINTEL CORP·Filed 2019·Granted Sep 19, 2023·2 cites·11 claims
- 3180US11587827B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2022·Granted Feb 21, 2023·0 cites·25 claims
- 3279US12376342B2Passivation layers for thin film transistorsINTEL CORP·Filed 2024·Granted Jul 29, 2025·0 cites·20 claims
- 3379US11916118B2Stacked source-drain-gate connection and process for forming suchINTEL CORP·Filed 2023·Granted Feb 27, 2024·0 cites·20 claims
- 3479US11699681B2Multi-chip module having a stacked logic chip and memory stackINTEL CORP·Filed 2019·Granted Jul 11, 2023·2 cites·20 claims
- 3579US11393818B2Stacked transistors with Si PMOS and high mobility thin film transistor NMOSINTEL CORP·Filed 2018·Granted Jul 19, 2022·2 cites·24 claims
- 3678US12255137B2Sideways vias in isolation areas to contact interior layers in stacked devicesINTEL CORP·Filed 2024·Granted Mar 18, 2025·0 cites·12 claims
- 3778US12224202B2Forming an oxide volume within a finINTEL CORP·Filed 2023·Granted Feb 11, 2025·0 cites·13 claims
- 3877US11640961B2III-V source/drain in top NMOS transistors for low temperature stacked transistor contactsINTEL CORP·Filed 2018·Granted May 2, 2023·2 cites·15 claims
- 3977US11251186B2Compute near memory with backend memoryINTEL CORP·Filed 2020·Granted Feb 15, 2022·1 cites·19 claims
- 4077US10832951B2Interconnect wires including relatively low resistivity coresINTEL CORP·Filed 2017·Granted Nov 10, 2020·1 cites·11 claims
- 4177US2024371700A1Backside contacts for semiconductor devicesINTEL CORP·Filed 2024·Application pending·0 cites
- 4276US11251076B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2020·Granted Feb 15, 2022·0 cites·20 claims
- 4375US2024304549A1Multi-height & multi-width interconnect line metallization for integrated circuit structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 4474US11569126B2Interconnect wires including relatively low resistivity coresINTEL CORP·Filed 2020·Granted Jan 31, 2023·0 cites·21 claims
- 4573US11672133B2Vertically stacked memory elements with air gapINTEL CORP·Filed 2019·Granted Jun 6, 2023·1 cites·19 claims
- 4673US2024234422A1Stacked forksheet transistorsINTEL CORP·Filed 2024·Application pending·0 cites
- 4772US10763161B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2019·Granted Sep 1, 2020·0 cites·20 claims
- 4871US11437405B2Transistors stacked on front-end p-type transistorsINTEL CORP·Filed 2018·Granted Sep 6, 2022·1 cites·25 claims
- 4971US10529619B2Conformal low temperature hermetic dielectric diffusion barriersINTEL CORP·Filed 2019·Granted Jan 7, 2020·0 cites·25 claims
- 5070US11869894B2Metallization structures for stacked device connectivity and their methods of fabricationINTEL CORP·Filed 2022·Granted Jan 9, 2024·0 cites·20 claims
Showing the top 50 of 98 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →