Inventor · disambiguated record
Hyung-Ock Kim
Also filed as: KIM HYUNG OCK
11 granted patents·2 pending applications·67 citations·filing 2007–2019
86Inventor score
Files withSAMSUNG ELECTRONICS CO LTD8KIM HYUNG-OCK2DO KYUNG TAE1KIM WOOK1KOREA ADVANCED INST SCI & TECH1
Top patents by PatentIndex Score
13 records- 0194US7948263B2Power gating circuit and integrated circuit including sameSAMSUNG ELECTRONICS CO LTD·Filed 2010·Granted May 24, 2011·34 cites·18 claims
- 0285US7755396B2Power network using standard cell, power gating cell, and semiconductor device using the power networkKOREA ADVANCED INST SCI & TECH·Filed 2007·Granted Jul 13, 2010·15 cites·6 claims
- 0382US8522188B2Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chipKIM HYUNG-OCK·Filed 2012·Granted Aug 27, 2013·9 cites·19 claims
- 0478US10817640B2Integrated circuit including different types of cells, and method and system of designing the sameSAMSUNG ELECTRONICS CO LTD·Filed 2019·Granted Oct 27, 2020·2 cites·19 claims
- 0573US8659316B2Power control circuit, semiconductor device including the sameKIM HYUNG OCK·Filed 2012·Granted Feb 25, 2014·5 cites·20 claims
- 0672US10599130B2Method and system for manufacturing an integrated circuit in consideration of a local layout effectSAMSUNG ELECTRONICS CO LTD·Filed 2018·Granted Mar 24, 2020·2 cites·17 claims
- 0749US10928442B2Computer implemented methods and computing systems for designing integrated circuits by considering back-end-of-lineSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Feb 23, 2021·0 cites·15 claims
- 0847US10817637B2System and method of designing integrated circuit by considering local layout effectSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Oct 27, 2020·0 cites·16 claims
- 0941US2013086536A1Method of generating standard cell library for dpl process and methods of producing a dpl mask and circuit pattern using the sameKIM WOOK·Filed 2012·Application pending·0 cites
- 1037US10424518B2Integrated circuit designing system and a method of manufacturing an integrated circuitSAMSUNG ELECTRONICS CO LTD·Filed 2017·Granted Sep 24, 2019·0 cites·15 claims
- 1137US10002219B2Method for placing parallel multiplierSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jun 19, 2018·0 cites·15 claims
- 1235US2012313693A1Semiconductor device, method and system with logic gate region receiving clock signal and body bias voltage by enable signalDO KYUNG TAE·Filed 2012·Application pending·0 cites
- 1334US10026471B2System-on-chip and electronic device having the sameSAMSUNG ELECTRONICS CO LTD·Filed 2016·Granted Jul 17, 2018·0 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Hyung-Ock Kim files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →