Inventor · disambiguated record
Ian L. Mcewen
Also filed as: MCEWEN IAN L
15 granted patents·114 citations·filing 1997–2016
92Inventor score
Top patents by PatentIndex Score
15 records- 0181US8117577B1Determining timing paths within a circuit block of a programmable integrated circuitVADI VASISHT M·Filed 2009·Granted Feb 14, 2012·16 cites·20 claims
- 0278US7367007B1Method of routing a design to increase the quality of the designXILINX INC·Filed 2005·Granted Apr 29, 2008·9 cites·11 claims
- 0377US9454630B1Graphical representation of integrated circuitsXILINX INC·Filed 2013·Granted Sep 27, 2016·7 cites·20 claims
- 0476US7949974B1Isolation verification within integrated circuitsXILINX INC·Filed 2008·Granted May 24, 2011·8 cites·10 claims
- 0575US10331837B1Device graphics rendering for electronic designsXILINX INC·Filed 2016·Granted Jun 25, 2019·3 cites·18 claims
- 0674US8104011B1Method of routing a design to increase the quality of the designSUNDARARAJAN PRASANNA·Filed 2008·Granted Jan 24, 2012·7 cites·19 claims
- 0772US7149997B1Routing with frame awareness to minimize device programming time and test costXILINX INC·Filed 2004·Granted Dec 12, 2006·17 cites·16 claims
- 0871US7058919B1Methods of generating test designs for testing specific routing resources in programmable logic devicesXILINX INC·Filed 2003·Granted Jun 6, 2006·15 cites·33 claims
- 0970US7299430B1Reducing design execution run time bit stream size for device testingXILINX INC·Filed 2005·Granted Nov 20, 2007·6 cites·20 claims
- 1067US8752075B1Method for data transportXILINX INC·Filed 2013·Granted Jun 10, 2014·3 cites·19 claims
- 1163US7480842B1Method and apparatus for reducing the number of test designs for device testingXILINX INC·Filed 2004·Granted Jan 20, 2009·9 cites·9 claims
- 1256US8082535B1Method and apparatus for testing programmable integrated circuitsMCEWEN IAN L·Filed 2009·Granted Dec 20, 2011·2 cites·9 claims
- 1344US6049224AProgrammable logic device with logic cells having a flexible input structureLUCENT TECHNOLOGIES INC·Filed 1997·Granted Apr 11, 2000·8 cites·24 claims
- 1442US8418221B1Methods of prioritizing routing resources to generate and evaluate test designs in programmable logic devicesYOUNG JAY T·Filed 2004·Granted Apr 9, 2013·0 cites·28 claims
- 1542US7234120B1Fault isolation in a programmable logic deviceXILINX INC·Filed 2004·Granted Jun 19, 2007·4 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →